Patents by Inventor Ching-Min Hou
Ching-Min Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11467847Abstract: The disclosure provides a restart control device and a restart control method. The restart control device is disposed in an electronic device. The electronic device includes a keyboard and a restart button. At least one assigned key of a plurality of keys of the keyboard is set. The restart control device determines whether the at least one assigned key is pressed, and determines whether the restart button is pressed. When determining that the restart button is pressed and the at least one assigned key is pressed, the restart control device provides a restart control signal to cause the electronic device to perform a restart operation. The disclosure can prevent an unnecessary restart operation due to a single restart button being mistyped.Type: GrantFiled: March 13, 2020Date of Patent: October 11, 2022Assignee: ITE Tech. Inc.Inventors: Ching-Min Hou, An-Chi Tsai
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Publication number: 20210208898Abstract: The disclosure provides a restart control device and a restart control method. The restart control device is disposed in an electronic device. The electronic device includes a keyboard and a restart button. At least one assigned key of a plurality of keys of the keyboard is set. The restart control device determines whether the at least one assigned key is pressed, and determines whether the restart button is pressed. When determining that the restart button is pressed and the at least one assigned key is pressed, the restart control device provides a restart control signal to cause the electronic device to perform a restart operation. The disclosure can prevent an unnecessary restart operation due to a single restart button being mistyped.Type: ApplicationFiled: March 13, 2020Publication date: July 8, 2021Applicant: ITE Tech. Inc.Inventors: Ching-Min Hou, An-Chi Tsai
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Patent number: 9684383Abstract: An electronic apparatus and a method for detecting status of keys thereof are provided. The electronic apparatus comprises a key module, a key control circuit, a conversion circuit with calibration mechanism and a processor. The key control circuit detects whether any of keys in the key module is pressed. If the detection result is affirmative, the press status of each of the keys is scanned by the key control circuit to obtain a coarse scan result. The conversion circuit with calibration mechanism is configured to perform the other system function of the electronic apparatus. When the processor determines that at least one of the keys is not pressed according the coarse scan result, the conversion circuit with calibration mechanism is switched to assist a re-scan operation of the press status of the at least one of the keys.Type: GrantFiled: April 27, 2016Date of Patent: June 20, 2017Assignee: ITE Tech. Inc.Inventors: Ching-Min Hou, An-Chi Tsai, Tzu-I Huang
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Publication number: 20170168588Abstract: An electronic apparatus and a method for detecting status of keys thereof are provided. The electronic apparatus comprises a key module, a key control circuit, a conversion circuit with calibration mechanism and a processor. The key control circuit detects whether any of keys in the key module is pressed. If the detection result is affirmative, the press status of each of the keys is scanned by the key control circuit to obtain a coarse scan result. The conversion circuit with calibration mechanism is configured to perform the other system function of the electronic apparatus. When the processor determines that at least one of the keys is not pressed according the coarse scan result, the conversion circuit with calibration mechanism is switched to assist a re-scan operation of the press status of the at least one of the keys.Type: ApplicationFiled: April 27, 2016Publication date: June 15, 2017Applicant: ITE Tech. Inc.Inventors: Ching-Min Hou, An-Chi Tsai, Tzu-I Huang
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Patent number: 8737156Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.Type: GrantFiled: October 22, 2012Date of Patent: May 27, 2014Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Publication number: 20130151832Abstract: A flash memory storage system includes a flash memory, a host and a controller is provided. The controller couples to the host and the flash memory, and restricts the host to access the flash memory according to a state of the host. When the host is in a booting state or in a resetting state, the controller allows the host to access the flash memory. After the host completes a booting process or a resetting process, the controller restricts the host to access the flash memory so as to protect a data stored by the flash memory. Besides, a data protection method for which applied to the above-mentioned storage system is also provided in the present invention.Type: ApplicationFiled: February 8, 2012Publication date: June 13, 2013Applicant: ITE Tech. Inc.Inventors: Chia-Yuan Chou, Ching-Min Hou
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Publication number: 20130100736Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.Type: ApplicationFiled: October 22, 2012Publication date: April 25, 2013Inventor: Ching-Min Hou
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Patent number: 8307168Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: GrantFiled: July 22, 2011Date of Patent: November 6, 2012Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Patent number: 8307167Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: GrantFiled: July 22, 2011Date of Patent: November 6, 2012Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Patent number: 8301846Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: GrantFiled: June 20, 2011Date of Patent: October 30, 2012Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Publication number: 20110276751Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: July 22, 2011Publication date: November 10, 2011Applicant: ITE TECH. INC.Inventor: Ching-Min Hou
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Publication number: 20110276739Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: July 22, 2011Publication date: November 10, 2011Applicant: ITE TECH. INC.Inventor: Ching-Min Hou
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Publication number: 20110252175Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: June 20, 2011Publication date: October 13, 2011Applicant: ITE TECH. INC.Inventor: Ching-Min HOU
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Patent number: 8024540Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: GrantFiled: June 14, 2010Date of Patent: September 20, 2011Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Patent number: 7818529Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: GrantFiled: November 19, 2007Date of Patent: October 19, 2010Assignee: ITE Tech. Inc.Inventor: Ching-Min Hou
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Publication number: 20100257300Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: June 14, 2010Publication date: October 7, 2010Applicant: ITE Tech. Inc.Inventor: Ching-Min Hou
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Patent number: 7685343Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signal is transmitted on a clock pin and a data signal is transmitted on a data pin. In each of the suspending intervals, the clock signal stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using a plurality of registers. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of the integrated circuit.Type: GrantFiled: March 29, 2007Date of Patent: March 23, 2010Assignee: ITE Tech. Inc.Inventors: Ching-Min Hou, Kung-Hsien Chu
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Publication number: 20090070516Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.Type: ApplicationFiled: November 19, 2007Publication date: March 12, 2009Applicant: ITE TECH. INC.Inventor: Ching-Min Hou
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Publication number: 20080155366Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signals is transmitted on a clock pin and a data signals is transmitted on a data pin. In each of the suspending intervals, the clock signals stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using any register. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of integrated circuit.Type: ApplicationFiled: March 29, 2007Publication date: June 26, 2008Applicant: ITE TECH. INC.Inventors: Ching-Min Hou, Kung-Hsien Chu
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Publication number: 20080122659Abstract: An embedded controller includes a keyboard interface, a keyboard signal conversion unit, a flash memory control unit, and a selection unit. When the selection unit couples the flash memory control unit to the keyboard interface according to an indication signal, a remote controller is coupled to the keyboard interface so as to input an input signal to the embedded controller through the keyboard interface. And the flash memory control unit decodes the input signal and writes it into a flash memory to change a data stored in the flash memory.Type: ApplicationFiled: February 9, 2007Publication date: May 29, 2008Applicant: ITE TECH. INC.Inventors: Ching-Min Hou, Po-Cheng Chen