Patents by Inventor Ching-Ming Lai

Ching-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10401288
    Abstract: A method comprises receiving an output signal of one of multiple detection channels. The method further includes color separating the output signal and generating a color-separated signal substantially only with the peaks corresponding to the detected signals with the principle emission in the emission spectrum range of the detection channel. The method further includes estimating a time-variant amplitude of the gradually decaying tail and removing the time-variant amplitude from the color-separated signal. The method further includes generating a corrected colored-separated signal with substantially only the peaks corresponding to the fluorescent dyes attached to the fragments in the sample.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 3, 2019
    Assignee: ANALOGIC CORPORATION
    Inventor: Ching Ming Lai
  • Publication number: 20190267298
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin Lin WU, Yu-Hsuan TSAI, Chang Chin TSAI, Lu-Ming LAI, Ching-Han HUANG
  • Patent number: 10354986
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Publication number: 20190214356
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Publication number: 20190165177
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHING, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 9920362
    Abstract: A method for determining an allelic ladder signal for DNA analysis includes obtaining a measured allelic ladder signal for an allelic ladder substance, which includes a plurality of fragments, obtaining a reference set of expected fragment sizes of fragments of the ladder substance, and generating a signal identifying whether a peak for a fragment size of the measured ladder signal is a true peak of the ladder substance based on the reference set of expected fragment sizes, wherein the allelic ladder signal for DNA analysis includes the true peaks identified in the signal.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: March 20, 2018
    Assignee: Analogic Corporation
    Inventor: Ching Ming Lai
  • Publication number: 20170315088
    Abstract: A sample processing apparatus (102) includes a plurality of processing stations (108) configured to process a sample that includes a DNA sample and an ILS substance carried by a sample carrier. One of the plurality of processing stations includes an electrophoresis processing station. The sample processing apparatus further includes an optical reader (110) that generates a plurality of DNA sample color group signals and an ILS signal based on a result of the electrophoresis processing station. One of the DNA sample color group signals includes at least the locus amelogenin X-peak. The sample processing apparatus further includes an ILS signal validator (112) that validates peaks of the ILS signal as true peaks of the ILS signal only if the amelogenin X-peak of the one of the DNA sample color group signals is found between two peaks of the ILS signal.
    Type: Application
    Filed: October 23, 2014
    Publication date: November 2, 2017
    Applicant: Analogic Corporation
    Inventor: Ching-Ming LAI
  • Patent number: 9611199
    Abstract: A method includes calibrating color bleed factors of optical detector channels of a sample processing apparatus through processing a color bleed calibration substance which includes a plurality of different size fragments replicated from different groups of DNA loci, wherein fragments in a same group are labeled with a same fluorescent dye, and fragments in different groups are labeled with different fluorescent dyes having different emission spectra, wherein the different size fragments are processed during different acquisition times.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Analogic Corporation
    Inventor: Ching Ming Lai
  • Publication number: 20160018333
    Abstract: A method includes calibrating color bleed factors of optical detector channels of a sample processing apparatus through processing a color bleed calibration substance which includes a plurality of different size fragments replicated from different groups of DNA loci, wherein fragments in a same group are labeled with a same fluorescent dye, and fragments in different groups are labeled with different fluorescent dyes having different emission spectra, wherein the different size fragments are processed during different acquisition times.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventor: Ching Ming LAI
  • Patent number: 9164039
    Abstract: A method includes calibrating color bleed factors of optical detector channels of a sample processing apparatus through processing a color bleed calibration substance which includes a plurality of different size fragments replicated from different groups of DNA loci, wherein fragments in a same group are labeled with a same fluorescent dye, and fragments in different groups are labeled with different fluorescent dyes having different emission spectra, wherein the different size fragments are processed during different acquisition times.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: October 20, 2015
    Assignee: Analogic Corporation
    Inventor: Ching Ming Lai
  • Patent number: 9030049
    Abstract: An alternating current (AC) to direct current (DC) converter device includes an AC-to-DC converter circuit, a step-down DC converter circuit, a controller, a first standby power converter circuit and a second standby power converter circuit. The AC-to-DC converter circuit is adapted to receive and perform an AC-to-DC conversion on an AC power so as to output a DC bus voltage. The step-down DC converter performs a step-down conversion on the DC bus voltage so as to output a main power voltage. The first standby power converter circuit performs a step-down conversion on the main power voltage so as to output a first standby DC voltage. The second standby power converter circuit performs a step-down conversion on the DC bus voltage to output a second standby DC voltage.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 12, 2015
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.
    Inventor: Ching-Ming Lai
  • Patent number: 8971058
    Abstract: A high-efficiency high step-up ratio direct current converter with an interleaved soft-switching mechanism is provided. The direct current converter includes a voltage-multiplier circuit and an active clamping circuit. The voltage-multiplier circuit includes two isolating transformers, two main switches disposed on a primary side of the two isolating transformers, four diodes disposed on a secondary side of the two isolating transformers and four capacitors disposed on the secondary side of two isolating transformers, configured to boost a voltage of a direct-current power to a desired voltage value. The active clamping circuit, electrically connected to the voltage-multiplier circuit, includes two active clamp switches and a clamp capacitor to lower a voltage surge of the two main switches so that the two main switches and the two active clamp switches can be soft switched on.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Allis Electric Co., Ltd.
    Inventors: Ching-Tsai Pan, Ming-Chieh Cheng, Ching-Ming Lai, Yen-Liang Chou, Chih-Hsing Fang, Wen-Wei Chan
  • Patent number: 8736110
    Abstract: A simplified multilevel DC converter circuit structure comprises a dual input DC power supply, a power control module and an AC side low-pass filter, wherein each of the dual input DC power supply supplies half of the rated DC voltage to the power control module, and the power control module is composed of six power switches, and different switching combinations of each power switch are controlled to convert a DC voltage to an output of an AC voltage, and two of the power switches of the power control module perform a low-frequency switching twice every cycle of the output voltage, and the withstand voltage is equal to the input voltage, and the remaining power switches perform the switching by a high frequency, and the withstand voltage is only half of the input voltage, such that a multilevel voltage can be outputted, and a low harmonic AC waveform can be outputted from the AC side low-pass filter.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 27, 2014
    Assignee: National Penghu University of Science and Technology
    Inventors: Yi-Hung Liao, Ching-Ming Lai
  • Publication number: 20140056032
    Abstract: A high-efficiency high step-up ratio direct current converter with an interleaved soft-switching mechanism is provided. The direct current converter includes a voltage-multiplier circuit and an active clamping circuit. The voltage-multiplier circuit includes two isolating transformers, two main switches disposed on a primary side of the two isolating transformers, four diodes disposed on a secondary side of the two isolating transformers and four capacitors disposed on the secondary side of two isolating transformers, configured to boost a voltage of a direct-current power to a desired voltage value. The active clamping circuit, electrically connected to the voltage-multiplier circuit, includes two active clamp switches and a clamp capacitor to lower a voltage surge of the two main switches so that the two main switches and the two active clamp switches can be soft switched on.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: ALLIS ELECTRIC CO., LTD.
    Inventors: Ching-Tsai Pan, Ming-Chieh Cheng, Ching-Ming Lai, Yen-Liang Chou, Chih-Hsing Fang, Wen-Wei Chan
  • Publication number: 20130273529
    Abstract: A method for determining an allelic ladder signal for DNA analysis includes obtaining a measured allelic ladder signal for an allelic ladder substance, which includes a plurality of fragments, obtaining a reference set of expected fragment sizes of fragments of the ladder substance, and generating a signal identifying whether a peak for a fragment size of the measured ladder signal is a true peak of the ladder substance based on the reference set of expected fragment sizes, wherein the allelic ladder signal for DNA analysis includes the true peaks identified in the signal.
    Type: Application
    Filed: December 30, 2010
    Publication date: October 17, 2013
    Applicant: Analogic Corporation
    Inventor: Ching Ming Lai
  • Publication number: 20130214177
    Abstract: A method includes calibrating color bleed factors of optical detector channels of a sample processing apparatus through processing a color bleed calibration substance which includes a plurality of different size fragments replicated from different groups of DNA loci, wherein fragments in a same group are labeled with a same fluorescent dye, and fragments in different groups are labeled with different fluorescent dyes having different emission spectra, wherein the different size fragments are processed during different acquisition times.
    Type: Application
    Filed: October 20, 2010
    Publication date: August 22, 2013
    Inventor: Ching Ming Lai
  • Patent number: 8493753
    Abstract: A photovoltaic powered system and an alternating current (AC) module thereof are disclosed. The photovoltaic powered system provides a direct current (DC) power through a photovoltaic module and converts the DC power into an AC power, which is grid-connected to an AC utility power. The AC module of the photovoltaic powered system produces a continuous quasi-sinusoidal current and the quasi-sinusoidal current is converted into a sinusoidal current. The high-frequency harmonic components of the sinusoidal current are filtered to produce a sinusoidal output current in phase with the AC utility power, thus realizing the maximum power point tracking (MPPT) of the photovoltaic module and feeding unity-power-factor power into the AC utility power.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: July 23, 2013
    Assignee: Allis Electric Co., Ltd.
    Inventors: Ching-Ming Lai, Ching-Tsai Pan, Chih-Hsing Fang, Wen-Wei Chan, Ming-Chieh Cheng
  • Publication number: 20130127248
    Abstract: An alternating current (AC) to direct current (DC) converter device includes an AC-to-DC converter circuit, a step-down DC converter circuit, a controller, a first standby power converter circuit and a second standby power converter circuit. The AC-to-DC converter circuit is adapted to receive and perform an AC-to-DC conversion on an AC power so as to output a DC bus voltage. The step-down DC converter performs a step-down conversion on the DC bus voltage so as to output a main power voltage. The first standby power converter circuit performs a step-down conversion on the main power voltage so as to output a first standby DC voltage. The second standby power converter circuit performs a step-down conversion on the DC bus voltage to output a second standby DC voltage.
    Type: Application
    Filed: June 13, 2012
    Publication date: May 23, 2013
    Applicants: LITE-ON TECHNOLOGY CORP., SILITEK ELECTRONIC (GUANGZHOU) CO., LTD.
    Inventor: CHING-MING LAI
  • Publication number: 20130090861
    Abstract: A method for verifying an ILS signal for DNA processing includes obtaining the ILS signal, determining acquisition times between peaks of the ILS signal, obtaining acquisition times between peaks in reference ILS information for the ILS signal, and verifying the ILS signal based on the ILS acquisition times and the reference ILS acquisitions times. An ILS signal processor (116) includes a false peak remover (208) that removes any false peaks in an ILS signal and a signal verifier (212) that verifies the ILS signal includes only true peaks based on reference ILS information for the ILS signal.
    Type: Application
    Filed: June 29, 2010
    Publication date: April 11, 2013
    Applicant: ANALOGIC CORPORATION
    Inventor: Ching Ming Lai