Patents by Inventor CHING-PEI SU

CHING-PEI SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070472
    Abstract: The present disclosure provides a packing method including following steps. Genetic algorithm is utilized to calculate multiple packing programs. Multiple candidate packing programs including all items are selected from the packing programs. Among each of the candidate packing programs, at least one of the items to be placed earlier is classified into a first subset, and at least another one of the items to be placed later is classified into a second subset. Among each of the candidate packing programs, a first packing for the first subset is maintained, and a second packing for the second subset is recalculated by using a greedy algorithm to generate an updated second packing.
    Type: Application
    Filed: September 14, 2022
    Publication date: February 29, 2024
    Inventors: Ying-Sheng LUO, Trista Pei-Chun CHEN, Li-Ya SU, Ching Hui LI
  • Patent number: 11610808
    Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Pei Su, Tung-I Lin
  • Publication number: 20210057270
    Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: YU-HUNG CHENG, CHENG-TA WU, YEUR-LUEN TU, CHING-PEI SU, TUNG-I LIN