Patents by Inventor Ching-Pin Lin
Ching-Pin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984422Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.Type: GrantFiled: February 23, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Hsien Huang, Yao-Chun Chuang, SyuFong Li, Ching-Pin Lin, Jun He
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Publication number: 20230187315Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.Type: ApplicationFiled: June 6, 2022Publication date: June 15, 2023Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
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Publication number: 20230178589Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. A guard ring is disposed in the dielectric layer and around the through via. The guard ring includes metal layers stacked along the first direction. The metal layers include first sidewalls and second sidewall. The first sidewalls form an inner sidewall of the guard ring. An overlap between the first sidewalls of the metal layers is less than about 10 nm. The overlap is along a second direction different than the first direction.Type: ApplicationFiled: June 3, 2022Publication date: June 8, 2023Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
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Publication number: 20230045422Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.Type: ApplicationFiled: February 23, 2022Publication date: February 9, 2023Inventors: Li-Hsien Huang, Yao-Chun Chuang, SyuFong Li, Ching-Pin Lin, Jun He
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Publication number: 20220376081Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: I-Chih CHEN, Ru-Shang HSIAO, Ching-Pin LIN, Chih-Mu HUANG, Fu-Tsun TSAI
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Patent number: 11437495Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: GrantFiled: January 25, 2021Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chih Chen, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai
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Publication number: 20220254739Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.Type: ApplicationFiled: September 21, 2021Publication date: August 11, 2022Inventors: Min-Feng KU, Yao-Chun CHUANG, Ching-Pin LIN, Cheng-Chien LI
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Patent number: 11145760Abstract: A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.Type: GrantFiled: September 25, 2019Date of Patent: October 12, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Kuan Jung Chen, I-Chih Chen, Chih-Mu Huang, Ching-Pin Lin, Sheng-Lin Hsieh
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Publication number: 20210210616Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: ApplicationFiled: January 25, 2021Publication date: July 8, 2021Inventors: I-Chih CHEN, Ru-Shang HSIAO, Ching-Pin LIN, Chih-Mu HUANG, Fu-Tsun TSAI
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Publication number: 20210066491Abstract: A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.Type: ApplicationFiled: September 25, 2019Publication date: March 4, 2021Inventors: Kuan Jung CHEN, I-Chih CHEN, Chih-Mu HUANG, Ching-Pin LIN, Sheng-Lin HSIEH
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Patent number: 10903336Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: GrantFiled: November 5, 2018Date of Patent: January 26, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chih Chen, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai
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Publication number: 20190165126Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.Type: ApplicationFiled: November 5, 2018Publication date: May 30, 2019Inventors: I-Chih CHEN, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai
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Patent number: 10153278Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.Type: GrantFiled: September 28, 2017Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Lin Hsieh, I-Chih Chen, Chih-Mu Huang, Ching-Pin Lin, Ru-Shang Hsiao, Ting-Chun Kuan
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Patent number: 10056455Abstract: A semiconductor device including a substrate, a gate stack, a pair of insulator structures, and source/drain materials is provided. The substrate has a plurality of recesses, wherein the plurality of recesses defines a protruded portion of the substrate having a channel region, and the protruded portion has a first side surface and a second side surface opposite to the first side surface. The gate stack is disposed on the protruded portion of the substrate. The pair of insulator structures are disposed within the plurality of recesses and respectively covering parts of the first side surface and the second side surface of the protruded portion, wherein the channel region is uncovered by the pair of insulator structures. The source/drain materials are disposed on the substrate in the plurality of recesses and on two opposing sides of the channel region, wherein the source/drain materials cover the pair of insulator structures.Type: GrantFiled: November 1, 2017Date of Patent: August 21, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Chun Kuan, I-Chih Chen, Chih-Mu Huang, Ching-Pin Lin, Fu-Tsun Tsai, Ru-Shang Hsiao
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Patent number: 8846768Abstract: Novel Uses of small molecules, particularly, triterpenoids and ingol diterpenes isolated from Euphorbia neriifolia, are disclosed herein. The triterpenoids are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating cancer; whereas the ingol diterpenes are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating thrombocytopenia.Type: GrantFiled: August 27, 2012Date of Patent: September 30, 2014Assignee: Mackay Memorial HospitalInventors: Yu-Jen Chen, Lie-Chwn Lin, Ching-Pin Lin
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Publication number: 20140056995Abstract: Novel Uses of small molecules, particularly, triterpenoids and ingol diterpenes isolated from Euphorbia neriifolia, are disclosed herein. The triterpenoids are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating cancer; whereas the ingol diterpenes are useful as lead compounds for manufacturing a medicament or a pharmaceutical composition for treating thrombocytopenia.Type: ApplicationFiled: August 27, 2012Publication date: February 27, 2014Applicant: Mackay Memorial HospitalInventors: YU-JEN CHEN, Lie-Chwn Lin, Ching-Pin Lin