Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: Embodiments of the present invention provide methods, systems, apparatuses, and computer program products for determining the contact edge roughness of a contact hole etched in a wafer. One embodiment provides a method comprising acquiring image data corresponding to the hole; based at least in part on the image data, determining a hole profile; determining an ideal shape for the hole based at least in part on the hole profile; and determining the contact edge roughness based at least in part on the hole profile and ideal shape. The hole profile may be configured to describe a distance from a reference point of the contact hole to an edge of the contact hole for each of a predetermined set of angles and the ideal shape may be described by a distance from a reference point of the ideal shape to an edge of the ideal shape for each predetermined angle.

Abstract: Methods for testing a special pattern and testing a probe card defect in wafer testing are provided. In the method for testing the special pattern, a wafer is divided into multiple testing partitions, in which each of the testing partitions includes multiple dies. The dies in each testing partition of the wafer are respectively tested by multiple sites of the probe card to obtain a testing map. Then, a number of the dies having defects and a number of the dies without defect within each of the testing partitions in the testing map are accumulated to construct chi-square test and calculate a maximum P-value. Finally, it is determined whether a minimum of the maximum P-values of all of the testing partitions is smaller than a certain predetermined threshold. If the minimum is smaller than the threshold, it is determined that the testing map of the wafer contains the special pattern.

Abstract: Methods for testing a special pattern and testing a probe card defect in wafer testing are provided. In the method for testing the special pattern, a wafer is divided into multiple testing partitions, in which each of the testing partitions includes multiple dies. The dies in each testing partition of the wafer are respectively tested by multiple sites of the probe card to obtain a testing map. Then, a number of the dies having defects and a number of the dies without defect within each of the testing partitions in the testing map are accumulated to construct chi-square test and calculate a maximum P-value. Finally, it is determined whether a minimum of the maximum P-values of all of the testing partitions is smaller than a certain predetermined threshold. If the minimum is smaller than the threshold, it is determined that the testing map of the wafer contains the special pattern.