Abstract: A solid state peripheral storage device receives an LSN address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units which are made out of solid state floating gate storage cells. In addition, a microsequencer controls the operation of the translation of the mapping of the LSN to PSN. Through the use of the mapping of LSN to PSN, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, the microsequencer has error recovery routines to further enhance the reliability of the peripheral device.

Abstract: A solid state peripheral storage device receives an LSN address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units which are made out of solid state floating gate storage cells. In addition, a microsequencer controls the operation of the translation of the mapping of the LSN to PSN. Through the use of the mapping of LSN to PSN, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, the microsequencer has error recovery routines to further enhance the reliability of the peripheral device.

Abstract: A solid state peripheral storage device receives an LSN address from a computer system and provides a mapping to a PSN data. The PSN data addresses memory units which are made out of solid state floating gate storage cells. In addition, a microsequencer controls the operation of the translation of the mapping of the LSN to PSN. Through the use of the mapping of LSN to PSN, defective sectors in the memory units can be mapped out and fresh, unused, defective-free sectors can then be replaced, all automatically, without user intervention. Finally, the microsequencer has error recovery routines to further enhance the reliability of the peripheral device.

Abstract: An electrically programmable and erasable floating gate memory array device is disclosed. The array has a plurality of column address lines, a plurality of row address lines, and a plurality of common source lines. Each of the memory cells has one terminal connected to one of the column address lines, another one connected to one of the row address lines, and a third connected to one of the common source lines. By appropriate selection circuit, a high voltage source can be connected to either the row address line to effect erasure of charges on the floating gate of the memory cells connected to the selected row address line or to the common source line to selectively program the memory cells connected to the associated common source line. In this manner, write disturbance can be limited.