Abstract: An apparatus and method for transferring data via DMA in data processing system from a host system to a transmission network. The transferred data is in longword format in which each longword consists of four bytes. Within a longword, valid bytes intended for transmission are contiguous. The adapter or I/O device includes a packet memory and a FIFO circuit interposed between the host system and packet memory to allow for differences in access speed of a host memory and the packet memory. The FIFO circuit contains four discrete FIFO circuits that are separately addressable for writing the bytes of each longword received from the host memory for storage in the FIFO circuit. The received longword is applied to a barrel shifter which aligns the first valid byte in the received longword with the one of the four discrete FIFO circuits containing a first available storage location at a current FIFO longword address.

Abstract: A method and corresponding apparatus for encoding and decoding additional status bits into an existing frame status byte transmitted as part of a packet of information in a communication network. The described scheme provides for the encoding and decoding of two additional status bits, without having to modify the packet format. In the disclosed embodiment of the invention, the additional status bits are used to convey information to a node processor concerning decryption processing of a received information packets.