Patents by Inventor Ching-Sheng Lin

Ching-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056712
    Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Unimicron Technology Corp.
    Inventors: Jun-Rui Huang, Chih-Chiang Lu, Yi-Pin Lin, Ching-Sheng Chen
  • Publication number: 20250041340
    Abstract: The present invention provides a method of treating targeted abnormal cells that are resistant, refractory, insensitive, non-responsive, or inadequately responsive to an ingredient, as well as cytotoxic cells used therein, comprising administering an effective amount of the ingredient-complexed cytotoxic cells to a subject with the disease.
    Type: Application
    Filed: December 12, 2022
    Publication date: February 6, 2025
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: CHING-WEN HSIAO, ZIH-FEI CHENG, TAI-SHENG WU, YAN-LIANG LIN, HAO-KANG LI, SAI-WEN TANG, HSIU-PING YANG, SHIH-CHIA HSIAO
  • Patent number: 7539068
    Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: May 26, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Chuan Wang, Ching-Sheng Lin, Chia-Pao Chang, Keng-Li Su
  • Publication number: 20080019192
    Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.
    Type: Application
    Filed: May 7, 2007
    Publication date: January 24, 2008
    Inventors: Min-Chuan Wang, Ching-Sheng Lin, Chia-Pao Chang, Keng-Li Su