Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.

Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.

Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.

Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.

Abstract: An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a plurality of source lines. A first plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same first row line and its source connected to the same first source line. A second plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same second row line, different from the first row line, and its source connected to the same first source line. Associated with each section is a plurality of bit latches, one for each column. Reprogramming data is stored in the bit latches. Data from the bit latches of one section are stored in the first plurality of floating gate memory cells.

Abstract: In the present invention a write protection circuit capable of being used in a memory card is disclosed. The write protection circuit receives an externally supplied write protect signal and generates a protection signal for use with an associated electrically alterable non-volatile memory. The write protection circuit has two non-volatile storage registers, each storing a single bit. Logic means receives a bit from a first register and passes the externally supplied write protect signal as the internally generated protection signal when the bit is in a "1" state. When the bit is in another state, the signal from the second register is used as the protection signal.