Patents by Inventor Ching-Shi Jenq
Ching-Shi Jenq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7199424Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: GrantFiled: January 23, 2006Date of Patent: April 3, 2007Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ting P. Yen
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Publication number: 20060131639Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: ApplicationFiled: January 23, 2006Publication date: June 22, 2006Inventors: Ching-Shi Jenq, Ting Yen
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Patent number: 7009244Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: GrantFiled: June 28, 2004Date of Patent: March 7, 2006Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ting P. Yen
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Patent number: 6967870Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.Type: GrantFiled: January 7, 2004Date of Patent: November 22, 2005Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Tien-Ler Lin
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Publication number: 20050146936Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.Type: ApplicationFiled: January 7, 2004Publication date: July 7, 2005Inventors: Ching-Shi Jenq, Tien-Ler Lin
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Publication number: 20050036393Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: ApplicationFiled: June 28, 2004Publication date: February 17, 2005Inventors: Ching-Shi Jenq, Ting Yen
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Patent number: 6621115Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.Type: GrantFiled: November 6, 2001Date of Patent: September 16, 2003Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ching Dong Wang
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Publication number: 20030087493Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.Type: ApplicationFiled: November 6, 2001Publication date: May 8, 2003Inventors: Ching-Shi Jenq, Ching Dong Wang
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Patent number: 6057575Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first edge and a second edge with a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom and has a first edge and a second edge aligned with the first edge and the second edge of the floating gate.Type: GrantFiled: July 2, 1998Date of Patent: May 2, 2000Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5886887Abstract: A voltage multiplier has a number of electrically-like stages. Each of the stages receives two input signals and a pump signal. The stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump signal and for separately pumping the first source/drain region and the gate of the first transistor by the pump signal. The two input signals are supplied to the first source/drain region and the gate of the first transistor, respectively. A first output signal is supplied from the second source/drain region of the first transistor, and from the first source/drain region of the first transistor. A voltage signal is supplied as the input signal of the first stage and a clock signal having a first phase is supplied to the first stage as the pump signal of the first stage.Type: GrantFiled: March 26, 1998Date of Patent: March 23, 1999Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5369609Abstract: An electrically programmable and erasable floating gate memory device has two substantially identical sections. Each section has a plurality of column address lines, a plurality of row lines and a plurality of source lines. A first plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same first row line and its source connected to the same first source line. A second plurality of floating gate memory cells has its drain connected to a different one of the column address line, its gate connected to the same second row line, different from the first row line, and its source connected to the same first source line. Associated with each section is a plurality of bit latches, one for each column. Reprogramming data is stored in the bit latches. Data from the bit latches of one section are stored in the first plurality of floating gate memory cells.Type: GrantFiled: November 12, 1992Date of Patent: November 29, 1994Assignee: Silicon Storage Technology, Inc.Inventors: Ping Wang, Ching-Shi Jenq
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Patent number: 5278087Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.Type: GrantFiled: October 15, 1992Date of Patent: January 11, 1994Assignee: Silicon Storage Technology, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5202850Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.Type: GrantFiled: August 21, 1991Date of Patent: April 13, 1993Assignee: Silicon Storage Technology, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5067108Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source and drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.Type: GrantFiled: January 22, 1990Date of Patent: November 19, 1991Assignee: Silicon Storage Technology, Inc.Inventor: Ching-Shi Jenq