Abstract: A pixel array substrate including pixel units is provided. Each of the pixel units includes a thin film transistor, a first insulating layer disposed on the thin film transistor, a common electrode disposed on the first insulating layer, a second insulating layer covering the common electrode, and a pixel electrode disposed on the second insulating layer. The first insulating layer includes a first via. The common electrode includes an opening and connects to the first via. The second insulating layer includes a second via and connects to the opening and the first via. The pixel electrode connects to the thin film transistor through the second via, the opening and the first via. The first via has two first sides opposite to each other and the opening has two third sides opposite to each other are aligned. A fourth side of the opening is not connected to the first via and the second via.

Abstract: A pixel array substrate including pixel units is provided. Each of the pixel units includes a thin film transistor, a first insulating layer disposed on the thin film transistor, a common electrode disposed on the first insulating layer, a second insulating layer covering the common electrode, and a pixel electrode disposed on the second insulating layer. The first insulating layer includes a first via. The common electrode includes an opening and connects to the first via. The second insulating layer includes a second via and connects to the opening and the first via. The pixel electrode connects to the thin film transistor through the second via, the opening and the first via. The first via has two first sides opposite to each other and the opening has two third sides opposite to each other are aligned. A fourth side of the opening is not connected to the first via and the second via.

Abstract: A pixel array substrate including pixel units is provided. Each of the pixel units includes a thin film transistor, a first insulating layer disposed on the thin film transistor, a common electrode disposed on the first insulating layer, a second insulating layer covering the common electrode, and a pixel electrode disposed on the second insulating layer. The first insulating layer includes a first via. The common electrode includes an opening and connects to the first via. The second insulating layer includes a second via and connects to the opening and the first via. The pixel electrode connects to the thin film transistor through the second via, the opening and the first via. The first via has two first sides opposite to each other and the opening has two third sides opposite to each other are aligned. A fourth side of the opening is not connected to the first via and the second via.

Abstract: A pixel array substrate including pixel units is provided. Each of the pixel units includes a thin film transistor, a first insulating layer disposed on the thin film transistor, a common electrode disposed on the first insulating layer, a second insulating layer covering the common electrode, and a pixel electrode disposed on the second insulating layer. The first insulating layer includes a first via. The common electrode includes an opening and connects to the first via. The second insulating layer includes a second via and connects to the opening and the first via. The pixel electrode connects to the thin film transistor through the second via, the opening and the first via. The first via has two first sides opposite to each other and the opening has two third sides opposite to each other are aligned. A fourth side of the opening is not connected to the first via and the second via.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Abstract: A method for preventing bubble defects in borophosphosilicate glass (BPSG) film is provided. A wafer for depositing borophosphosilicate glass (BPSG) film is loaded in deposition chamber. After the wafer is properly positioned, the wafer is heated to a predetermined temperature. A process gas is introduced from the gas distribution system to the deposition chamber. A selected pressure of the deposition chamber is set and maintained throughout deposition process. After deposition of the BPSG film, the wafer is loaded out the chamber. Subsequently, helium gas is introduced to purge the liquid injection valve and delivery path. After pumping out the purge gas, the another wafer is then loaded in the chamber for depositing BPSG film.