Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

Abstract: In one example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented longitudinal along the antenna radome. In another example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented transverse along the antenna radome.

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: In one example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented longitudinal along the antenna radome. In another example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented transverse along the antenna radome.

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.

Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

Abstract: In one example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented longitudinal along the antenna radome. In another example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented transverse along the antenna radome.

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.

Abstract: In one example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented longitudinal along the antenna radome. In another example, an antenna radome may have at least a first face that includes a plurality of surface features, where the plurality of surface features may include at least a first ridge and at least a first depression, and where the plurality of surface features may be oriented transverse along the antenna radome.