Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

Abstract: A loop gain calibration apparatus has an exciting signal generator, an exciting signal extracting circuit, and a loop gain control circuit. The exciting signal generator generates a first exciting signal and injects the first exciting signal into a timing recovery loop while the timing recovery loop is operating in response to a reception signal received under a normal reception mode. The exciting signal extracting circuit extracts a second exciting signal from the timing recovery loop after the first exciting signal is injected into the timing recovery loop. The loop gain control circuit receives the first exciting signal from the exciting signal generator, receives the second exciting signal from the exciting signal extracting circuit, and controls a loop gain of the timing recovery loop according to the first exciting signal and the second exciting signal.

Abstract: A wireless communication receiver includes a first signal processing block, a phase noise compensation apparatus, and a second signal processing block. The first signal processing block is arranged for generating a first processed output by processing a reception signal, wherein the first signal processing block includes a channel estimation unit arranged for performing channel estimation. The phase noise compensation apparatus is arranged for receiving the first processed output and generating a second processed output by performing phase noise compensation according to the received first processed output. The second signal processing block is arranged for receiving the second processed output and processing the received second processed output.

Abstract: A wireless communication receiver includes a first signal processing block, a phase noise compensation apparatus, and a second signal processing block. The first signal processing block is arranged for generating a first processed output by processing a reception signal, wherein the first signal processing block includes a channel estimation unit arranged for performing channel estimation. The phase noise compensation apparatus is arranged for receiving the first processed output and generating a second processed output by performing phase noise compensation according to the received first processed output. The second signal processing block is arranged for receiving the second processed output and processing the received second processed output.