Abstract: A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Abstract: A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.

Abstract: A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.

Abstract: A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

Abstract: A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

Abstract: A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

Abstract: A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

Abstract: A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.