Patents by Inventor Ching-Sung Ho
Ching-Sung Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699696Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.Type: GrantFiled: March 31, 2021Date of Patent: July 11, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Juin Jei Liou, Wenqiang Song, Ching-Sung Ho
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Patent number: 11621262Abstract: A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes.Type: GrantFiled: March 24, 2021Date of Patent: April 4, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Juin Jei Liou, Feibo Du, Ching-Sung Ho
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Patent number: 11538899Abstract: A semiconductor device including a substrate and a capacitor is provided. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The first electrode has a plurality of hemispherical recesses. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. Surfaces of the hemispherical recesses are in direct contact with the insulating layer.Type: GrantFiled: May 5, 2021Date of Patent: December 27, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ching-Sung Ho, Jia-Horng Tsai
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Publication number: 20220310780Abstract: A semiconductor device including a substrate and a capacitor is provided. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The first electrode has a plurality of hemispherical recesses. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. Surfaces of the hemispherical recesses are in direct contact with the insulating layer.Type: ApplicationFiled: May 5, 2021Publication date: September 29, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ching-Sung Ho, Jia-Horng Tsai
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Publication number: 20220293585Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.Type: ApplicationFiled: March 31, 2021Publication date: September 15, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Juin Jei Liou, Wenqiang Song, Ching-Sung Ho
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Publication number: 20220271029Abstract: A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes.Type: ApplicationFiled: March 24, 2021Publication date: August 25, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Juin Jei Liou, FEIBO DU, Ching-Sung Ho
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Patent number: 11335691Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: GrantFiled: February 22, 2021Date of Patent: May 17, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Publication number: 20210175237Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Patent number: 10971501Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: GrantFiled: May 29, 2019Date of Patent: April 6, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Publication number: 20200328215Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: ApplicationFiled: May 29, 2019Publication date: October 15, 2020Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Patent number: 7248707Abstract: A plug detection circuit. The detected circuit is disposed in an electronics device with an earphone jack, accepting plugs with a plurality of conductive rings. The detection circuit has a plurality of pins, wherein a first pin detects, and outputs a first logic potential, and a second pin detects the potentials at the conductive rings and outputs a second logic potential. The detection circuit determines the type of earphone connected to the earphone jack.Type: GrantFiled: July 30, 2003Date of Patent: July 24, 2007Assignee: High Tech Computer Corp.Inventors: Yu-Chun Peng, Ching-Sung Ho, Su-Hong Tseng, Hsi-Cheng Yeh
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Publication number: 20050090141Abstract: A plug detection circuit. The detected circuit is disposed in an electronics device with an earphone jack, accepting plugs with a plurality of conductive rings. The detection circuit has a plurality of pins, wherein a first pin detects, and outputs a first logic potential, and a second pin detects the potentials at the conductive rings and outputs a second logic potential. The detection circuit determines the type of earphone connected to the earphone jack.Type: ApplicationFiled: July 30, 2003Publication date: April 28, 2005Inventors: Yu-Chun Peng, Ching-Sung Ho, Su-Hong Tseng, Hsi-Cheng Yeh
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Publication number: 20040081297Abstract: A method for answering a call from a remote terminal with a smart phone. The method comprises the steps of pre-storing a sound clip in the smart phone, receiving the call and acquiring a caller identity delivered therewith from the remote terminal, generating a selection signal corresponding to the caller identity, and selecting a voice signal derived from a microphone or from the sound clip to be transmitted to the remote terminal according to the selection signal.Type: ApplicationFiled: August 20, 2003Publication date: April 29, 2004Inventors: Ching-sung Ho, Su-Hong Tseng, Hsi-Cheng Yeh, Chan-Li Liang