Patents by Inventor Ching-Te K. Chuang
Ching-Te K. Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8526219Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: GrantFiled: February 7, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Patent number: 8405129Abstract: A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: GrantFiled: April 18, 2012Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Publication number: 20120205721Abstract: A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: ApplicationFiled: April 18, 2012Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Publication number: 20120185817Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: ApplicationFiled: February 7, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Patent number: 8217427Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: GrantFiled: October 2, 2007Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Patent number: 8139400Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: GrantFiled: January 22, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Patent number: 8086917Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.Type: GrantFiled: August 17, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Saibal Mukhopadhyay
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Publication number: 20110173577Abstract: Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.Type: ApplicationFiled: February 1, 2008Publication date: July 14, 2011Applicant: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fook-Luen Heng, Rouwaida Kanj, Keunwoo Kim, Jin-Fuw Lee, Saibal Mukhopadhyay, Sani Richard Nassif, Rama Nand Singh
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Patent number: 7956669Abstract: A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.Type: GrantFiled: April 15, 2005Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Koushik K. Das, Keunwoo Kim
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Patent number: 7673195Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.Type: GrantFiled: October 3, 2007Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Saibal Mukhopadhyay
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Patent number: 7642864Abstract: A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals.Type: GrantFiled: January 29, 2008Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Tae-Hyoung Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M. Rao, Shao-yi Wang
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Publication number: 20090310430Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.Type: ApplicationFiled: August 17, 2009Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te K. Chuang, Jae-Joon Kim, Saibal Mukhopadhyay
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Publication number: 20090302354Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor.Type: ApplicationFiled: October 2, 2007Publication date: December 10, 2009Applicant: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jante Benedict Kuang, Hung C. Ngo
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Publication number: 20090190426Abstract: The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Applicant: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Niladri N. Mojumder, Saibal Mukhopadhyay
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Publication number: 20090189703Abstract: A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Applicant: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Tae-Hyoung Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M. Rao, Shao-yi Wang
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Publication number: 20090185409Abstract: A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: International Business Machines CorporationInventors: Aditya Bansal, Ching-Te K. Chuang, Jae-Joon Kim, Shih-Hsien Lo, Rahul M. Rao
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Patent number: 7548822Abstract: Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.Type: GrantFiled: July 13, 2007Date of Patent: June 16, 2009Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Amlan Ghosh, Jae-Joon Kim, Rahul M. Rao
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Publication number: 20090091346Abstract: A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Applicant: International Business Machines CorporationInventors: Ching-Te K. Chuang, Jae-Joon Kim, Saibal Mukhopadhyay
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Publication number: 20090018787Abstract: Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te K. Chuang, Amlan Ghosh, Jae-Joon Kim, Rahul M. Rao
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Patent number: 7085798Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.Type: GrantFiled: June 10, 2002Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Jae-Joon Kim, Ching-Te K. Chuang, Rajiv V. Joshi, Kaushik Roy