Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: A panel for an organic electroluminescent device is disclosed, which has a substrate having a first conducting area, a second conducting area, a third conducting area, and an active area; wherein active area locates between first conducting area and second conducting area; third conducting area locates at one side of active area; first conducting area, second conducting area, third conducting area and active area are integrated together on the surface of substrate; and third conducting area locates adjacent to first conducting area, second conducting area, and active area; a plurality of first conducting lines located in first conducting area on the substrate, a plurality of second conducting lines located in second conducting area on the substrate, and a plurality of third conducting lines located in third conducting area on the substrates.

Abstract: A novel nickel self-aligned silicide (SALICIDE) process technology (80) adapted for CMOS devices (54) with physical gate lengths of sub-40 nm. The excess silicidation problem (52) due to edge effect is effectively solved by using a low-temperature, in-situ formed Ni-rich silicide, preferably formed in a temperature range of 260-310° C. With this new process, excess poly gate silicidation is prevented. Island diode leakage current and breakdown voltage are also improved.

Abstract: Two barrier layers are used for a via or contact. A thin CVD barrier (124) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole (106). A sputter etch is then performed to remove the CVD barrier (124) at the bottom of the via/contact. A second barrier (126) is deposited after the sputter etch. The second barrier (126) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.

Abstract: Two barrier layers are used for a via or contact. A thin CVD barrier (124) (e.g., SiN, TiSiN, TaSiN, etc.) is deposited over a structure including within a via or contact hole (106). A sputter etch is then performed to remove the CVD barrier (124) at the bottom of the via/contact. A second barrier (126) is deposited after the sputter etch. The second barrier (126) comprises a lower resistivity barrier such as Ta, Ti, Mo, W, TaN, WN, MoN or TiN since the second barrier remains at the bottom of the via or contact. A metal fill process can then be performed.

Abstract: A post-liner/barrier/seed deposition sputter etch is used to remove an overhang portion (111) of a physical vapor deposited (PVD) film (110, 112, 214). A PVD process typically results in a liner/barrier (110,214) or seed (112) layer having thicker overhang portion (111) at the upper corners of a trench (108), via (106), or contact (212). A post deposition sputter etch using low bias is used to reduce the thickness of the overhang portion (111) and avoid a seam in a subsequent fill process.