Abstract: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: A method for forming via openings or contact holes with improved aspect ratios by using a deep UV photoresist is described. In the method, after a deep UV photoresist layer is deposited on top of a thick oxide layer, the deep UV photoresist layer is pre-treated by a curing process with UV radiation for a time period of at least 1 min, and preferably between about 1 min and about 10 min at a temperature of at least 100° C., and preferably at least 160° C. The curing process stabilizes the structure of the deep UV photoresist material and thus reduces the formation of fluorocarbon polymers by the carbon component in the photoresist material and the fluorine component in the etchant gas, and subsequently, reduces the coating of such fluorocarbon polymers at the bottom of the via openings which would otherwise stop the etching process during via or contact formation.

Abstract: A method for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening; partially removing the photo-sensitive resinous layer to form an at least partially filled via plug; photo-curing the via plug such that an activating light source causes a polymer cross-linking chemical reaction; and, forming a trench line opening disposed substantially over the at least one via opening using a trench line photoresist to pattern the trench line opening.

Abstract: A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80° C. The wafer is then cooled in a room temperature air for a sufficient length of time until the temperature of the wafer reaches substantially room temperature. The wafer is then rinsed in a rinsing step that includes a quick dump rinse and a final rinse with deionized water that is maintained at a temperature not higher than room temperature without first exposing the wafer to a buffer solvent such as that required in a conventional wet dip method.

Abstract: A method for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening; partially removing the photo-sensitive resinous layer to form an at least partially filled via plug; photo-curing the via plug such that an activating light source causes a polymer cross-linking chemical reaction; and, forming a trench line opening disposed substantially over the at least one via opening using a trench line photoresist to pattern the trench line opening.

Abstract: A method for forming via openings or contact holes with improved aspect ratios by using a deep UV photoresist is described. In the method, after a deep UV photoresist layer is deposited on top of a thick oxide layer, the deep UV photoresist layer is pre-treated by a curing process with UV radiation for a time period of at least 1 min, and preferably between about 1 min and about 10 min at a temperature of at least 100° C., and preferably at least 160° C. The curing process stabilizes the structure of the deep UV photoresist material and thus reduces the formation of fluorocarbon polymers by the carbon component in the photoresist material and the fluorine component in the etchant gas, and subsequently, reduces the coating of such fluorocarbon polymers at the bottom of the via openings which would otherwise stop the etching process during via or contact formation.

Abstract: A plasma etching method for improving an aspect ratio including an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device having at least a first underlying etching stop layer and at least a second etching stop layer overlying the oxide containing insulating layer; providing a patterned photoresist layer exposing an uppermost layer of the substrate for plasma etching; plasma etching through a thickness of at least a portion of the substrate; exposing the substrate to a polymerizing radiation source in at least a first curing process to initiate polymer cross-linking reactions; and plasma etching through at least another portion of a thickness of the substrate.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.

Abstract: A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80° C. The wafer is then cooled in a room temperature air for a sufficient length of time until the temperature of the wafer reaches substantially room temperature. The wafer is then rinsed in a rinsing step that includes a quick dump rinse and a final rinse with deionized water that is maintained at a temperature not higher than room temperature without first exposing the wafer to a buffer solvent such as that required in a conventional wet dip method.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.