Patents by Inventor Ching Tseng

Ching Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015054
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Publication number: 20250015080
    Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Wei Tseng, Jiun-Ming Kuo, Yuan-Ching Peng, Kuo-Yi Chao
  • Publication number: 20250002765
    Abstract: A low thermal shrinkage separator and a method for manufacturing thereof is disclosed. The method comprises providing a porous polyolefin substrate with a plurality of porous structures on surfaces and interiors thereof, and applying a prescursor solution comprising a titanium alkoxide and hexamethyldisilazane and subsequently applying an alcohol solution to form a low thermal shrinkage thin film formed on the surfaces and the sidewalls of the porous structures of the porous polyolefin substrate. The present method can enhance the low thermal shrinkage and electrolyte wettability of the separator.
    Type: Application
    Filed: November 3, 2023
    Publication date: January 2, 2025
    Applicant: BenQ Materials Corporation
    Inventors: TETSUYA OKAZAKI, WEN-HSIN YANG, CHUNG-CHING TSENG
  • Publication number: 20240404953
    Abstract: Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 5, 2024
    Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
  • Publication number: 20240379412
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a first source/drain feature, a first dielectric layer over the first source/drain feature, and a source/drain contact disposed in the first dielectric layer and over the first source/drain feature. The method further includes depositing a second dielectric layer over the source/drain contact and the first dielectric layer, forming a source/drain contact via opening through the second dielectric layer to expose the source/drain contact, depositing a sacrificial plug in the source/drain contact via opening, depositing a third dielectric layer over the second dielectric layer and the sacrificial plug, forming a trench in the third dielectric layer to expose the sacrificial plug, removing the sacrificial plug to expose the source/drain contact via opening, and after the removing of the sacrificial plug, forming an integrated conductive feature into the trench and the exposed source/drain contact via opening.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ya-Ching Tseng, Chang-Wen Chen, Po-Hsiang Huang
  • Publication number: 20240379584
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20240369885
    Abstract: A display device includes a substrate, a semiconductor, an electrode, a first conductive layer and a second conductive layer. The semiconductor is disposed on the substrate. The electrode is disposed on the substrate. The electrode is electrically connected to the semiconductor. The first conductive layer is overlapped with the electrode. The first conductive layer has a first opening. The second conductive layer is overlapped with the electrode. The second conductive layer has a second opening. The second conductive layer is closer to the substrate than the first conductive layer, and an area of the second opening is greater than an area of the first opening.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Patent number: 12125851
    Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Wei Tseng, Jiun-Ming Kuo, Yuan-Ching Peng, Kuo-Yi Chao
  • Patent number: 12125828
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 22, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240342054
    Abstract: A health care device illustrated has a low-frequency wave emitter, a low-frequency waveguide and a plant essential oil carrier disposed between the low-frequency wave emitter and the low-frequency waveguide. The low-frequency wave emitter emits a low-frequency wave with a predetermined frequency, and the low-frequency wave firstly passes through the plant essential oil carrier, and then propagates to the low-frequency waveguide. Next, energy of the low-frequency wave is focused in the low-frequency waveguide, and then the low-frequency wave is emitted out from the low-frequency waveguide. A health care method illustrated emits the low-frequency wave with the predetermined frequency to a belly button of a user by using the health care device. The health care device and method increase contents of NAD+ in blood of the user, and achieve effects of convenient operation, accurate use position identification, and non-invasive and non-contact health care.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 17, 2024
    Inventors: MING-SHUN LEE, CHIN-SUNG TSENG, HSU-HUI TSENG, HSIEN-CHING TSENG, WEI-LONG LEE
  • Publication number: 20240341705
    Abstract: A mobile tomosynthesis imaging equipment includes an adjustment mechanism, a light source, an image receptor and a mobile base. The adjustment mechanism is connected between the light source and the image receptor. The adjustment mechanism includes a rotating shaft. The light source, movably connected to the adjustment mechanism, is rotated about the rotating shaft and moved in a first direction with respect to the rotating shaft. The image receptor, movably connected to the adjustment mechanism, is rotated about the rotating shaft and moved in a second direction with respect to the rotating shaft. The mobile base, movably disposed to a bottom of the adjustment mechanism, is to move the adjustment mechanism, the light source and the image receptor, and to move the rotating shaft in a third direction.
    Type: Application
    Filed: July 11, 2023
    Publication date: October 17, 2024
    Inventors: CHIA-HAO CHANG, SHENG-PIN TSENG, YU-CHING NI
  • Patent number: 12113382
    Abstract: A charging control apparatus provides a supply power to first and second mobile devices. Each of the first and the second mobile device includes a mobile charging circuit and a battery. The charging control apparatus includes a switching power converter for converting an input power to the supply power, and a conversion control circuit for controlling the switching power converter according to the following steps: S1: controlling the switching power converter, so as to establish a current versus voltage characteristic curve corresponding to the supply power; and S2: determining a charging mode combinations of the first and the second mobile device and/or adjusting a supply voltage of the supply power to charge the battery of each mobile device according to the current versus voltage characteristic curve, so as to reduce a voltage drop of each mobile device as well as the power loss.
    Type: Grant
    Filed: November 6, 2021
    Date of Patent: October 8, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Shih-Hsin Tseng, Tseng-Chuan Wu, Po-Ching Lee
  • Publication number: 20240315017
    Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: WEICHANG LIU, Wang Xiang, CHIA CHING HSU, Yung-Lin Tseng, Shen-De Wang
  • Patent number: 12086080
    Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: George Chrysos, Bhargavi Narayanasetty, Jesus Corbal, Ching-Kai Liang, Chinmay Ashok, Francis Tseng
  • Patent number: 12072587
    Abstract: A display device includes a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The first slit and the second slit are overlapped with the pixel electrode.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: August 27, 2024
    Assignee: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Publication number: 20240266209
    Abstract: A semiconductor device includes a fin extending from a substrate and including a first fin end, a separation structure separating the first fin end from an adjacent fin end of another fin, a dummy gate spacer along sidewalls of the separation structure and the fin, a first epitaxial source/drain region in the fin and adjacent the separation structure, and a residue of a dummy gate material in a corner region between the dummy gate spacer and the first fin end. The first fin end protrudes from the dummy gate spacer into the separation structure. The residue of the dummy gate material separates the first epitaxial source/drain region from the separation structure and is triangle shaped.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Inventors: Chih-Han LIN, Kuei-Yu KAO, Shih-Yao LIN, Ke-Chia TSENG, Min Chiao LIN, Hsien-Chung HUANG, Chun-Hung CHEN, Guan Kai HUANG, Chao-Cheng CHEN, Chen-Ping CHEN, Ming-Ching CHANG
  • Patent number: 12051767
    Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: July 30, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
  • Publication number: 20240192734
    Abstract: This application is directed to a display assistant device that acts as a voice-activated user interface device. The display assistant device includes a base, a screen and a speaker. The base is configured for sitting on a surface. The screen has a rear surface and is supported by the base at the rear surface. A bottom edge of the screen is configured to be held above the surface by a predefined height, and the base is substantially hidden behind the screen from a front view of the display assistant device. The speaker is concealed inside the base and configured to project sound substantially towards the front view of the display assistant device.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 13, 2024
    Applicant: Google LLC
    Inventors: James Castro, Marc Davidson, Chih-Min Chien, Daniel Corbalan, Carl Cepress, Liang Ching Tseng
  • Publication number: 20240184340
    Abstract: In a display assistant device, a speaker is mounted in a waveguide structure which is at least partially disposed beneath a display screen. The waveguide structure is mounted in an exterior housing which includes speaker grills distributed on a plurality of surfaces of the exterior housing, permitting sound waves from the speaker to be projected outside the exterior housing. A cover structure is disposed on top of the waveguide structure to conceal the waveguide structure and speaker within the exterior housing. The cover structure has a tilted bottom surface configured to be suspended above the waveguide structure and to be separated by a first space. Sound waves projected from an upper portion of the speaker are reflected by the tilted bottom surface and are guided through the first space to exit the device from a speaker grill portion located on a rear side of the exterior housing.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 6, 2024
    Applicant: Google LLC
    Inventors: James Nelson Castro, Carl Alexander Cepress, Liang Ching Tseng, Darren Torrie, Frances Maria Hui Hong Kwee, Rex Pinegar Price
  • Publication number: 20240162618
    Abstract: An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, a first radiation element, a second radiation element, a parasitic radiation element, a tuning circuit, and a nonconductive support element. The metal mechanism element has a slot. The metal mechanism element includes a first grounding portion and a second grounding portion. The slot is positioned between the first grounding portion and the second grounding portion. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The parasitic radiation element is coupled to the ground element. The parasitic radiation element is adjacent to the first radiation element and the second radiation element. The tuning circuit is coupled between the first grounding portion and the second grounding portion of the metal mechanism element.
    Type: Application
    Filed: October 18, 2023
    Publication date: May 16, 2024
    Inventors: Wei-Chung CHANG, Shang-Ching TSENG