Abstract: A load detection apparatus which can be used for detecting loads of various kinds of peripheral devices. The present apparatus utilizes a compared result of a load potential and a reference potential to generate a high/low level signal output to adjust the load potential and make the load potential thus have a small fluctuation to achieve the purpose of load detection and maintain the peripheral devices working normally and uninterruptedly. The present apparatus can be used for detecting loads of various kinds of peripheral devices by properly choosing and replacing the values of the reference potential and other circuit element quantities.

Abstract: A buffer/driver is arranged in parallel between the data sending terminal and the data receiving terminal of a data transmission system. The SETUP time and HOLD time requirements of the data receiving terminal may be satisfied at the same time in accordance with the present invention. A low end, which has medium amount of time delay, buffer/driver may be used in this present invention to achieve a high performance of the data transmission which is usually possible in the past through the utilization of a high end buffer/driver, which has extremely small amount of time delay.

Abstract: An apparatus for altering the operating clock frequency of a computer system comprises an input port, a plurality of output ports, and instructing means coupled together by a bus. Latching means and gating means are coupled to CPU and the output ports to control the clock signal received. The input port receives a change frequency signal. In response, the CPU executes the instructions from the instructing means to store the contents of the CPU's internal registers into memory. The CPU then generates a frequency select signal and a reset signal that resets itself. The latch means stores and outputs the frequency select signal to the gating means. The gating means uses the frequency select signal to output one of a plurality of different frequency clock signals received at its select input as the operating clock input of the CPU. The CPU thereafter operates under the newly gated clock signal. After the CPU reset is complete, the CPU reloads its internal registers with the information stored within the memory.

Abstract: A memory system capable of incorporating defective memory chips is provided. The system includes a first memory chip having a first data signal line and being logically divided into an upper half and a lower half, a controlling circuit responsive to a first indicative address signal and an address strobe signal for outputting therefrom a second indicative address signal and a first and a second output enabling signals, and a second memory chip being logically divided into an upper and a lower halves and having a second data signal line electrically connected to the first data signal line so that only one of the first and second chips is accessible at any time.

Abstract: A clock switching circuit comprises a multiplexer, a gate, a first detector, a second detector and a state machine. The multiplexer receives two clock signals and outputs one of them through the gate. The first detector is coupled to the output of the multiplexer and the second detector is coupled to the output of the gate. The state machine controls the output of the gate and the multiplexer in response to signals from the first and second detector, and prevent glitches from being output by the gate.