Abstract: A method and a system for accelerating verification procedure for an image file are provided. In the method, the system retrieves an image file from a first non-volatile memory, and calculates a hash value with respect to the image file. A combination of the hash value, a public key and a digital signature is compared with another hash value, public key and digital signature backup in a second non-volatile memory. A comparison result is generated for verifying the image file in the first non-volatile memory. After the image file is verified, the system can load the image file. Instead of the conventional technology that uses digital signature to verify the image file, the present method can effectively accelerate the verification procedure.

Abstract: A debugging management platform and an operating method for the same are provided. In the operating method, the debugging management platform operates a debugging agent service for establishing a debugging channel between a software development platform and a test platform. When receiving debugging packets are issued by the software development platform or the test platform, the debugging agent service analyzes the debugging packets and checks if the debugging packets meet an information security standard. The debugging packets are forwarded to the test platform or the software development platform if the debugging packets meet the information security standard. If the debugging packets do not meet the information security standard, the debugging packets are not forwarded, so as to ensure information security of the debugging packets that are forwarded between different environments.

Abstract: The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.

Abstract: A debugging management platform and an operating method for the same are provided. In the operating method, the debugging management platform operates a debugging agent service for establishing a debugging channel between a software development platform and a test platform. When receiving debugging packets are issued by the software development platform or the test platform, the debugging agent service analyzes the debugging packets and checks if the debugging packets meet an information security standard. The debugging packets are forwarded to the test platform or the software development platform if the debugging packets meet the information security standard. If the debugging packets do not meet the information security standard, the debugging packets are not forwarded, so as to ensure information security of the debugging packets that are forwarded between different environments.

Abstract: The application discloses a verification method and system. The verification method is for verifying content of a first volatile read-write memory of a chip. A first non-volatile read-write memory of the chip stores a firmware image, including predetermined calculation value. The chip includes a second volatile read-write memory. The verification method includes: at a bootloader mode, loading a first portion and a second portion of the firmware image to the first volatile read-write memory and the second volatile read-write memory respectively; performing a first specific operation to the first portion and the second portion to obtain a first calculation value; performing a second specific operation to the first calculation value to obtain a second calculation value and storing the second calculation value in the second volatile read-write memory.

Abstract: The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.

Abstract: A method and a system for accelerating verification procedure for an image file are provided. In the method, the system retrieves an image file from a first non-volatile memory, and calculates a hash value with respect to the image file. A combination of the hash value, a public key and a digital signature is compared with another hash value, public key and digital signature backup in a second non-volatile memory. A comparison result is generated for verifying the image file in the first non-volatile memory. After the image file is verified, the system can load the image file. Instead of the conventional technology that uses digital signature to verify the image file, the present method can effectively accelerate the verification procedure.

Abstract: The application discloses a verification method and system. The verification method is for verifying content of a first volatile read-write memory of a chip. A first non-volatile read-write memory of the chip stores a firmware image, including predetermined calculation value. The chip includes a second volatile read-write memory. The verification method includes: at a bootloader mode, loading a first portion and a second portion of the firmware image to the first volatile read-write memory and the second volatile read-write memory respectively; performing a first specific operation to the first portion and the second portion to obtain a first calculation value; performing a second specific operation to the first calculation value to obtain a second calculation value and storing the second calculation value in the second volatile read-write memory.