Abstract: A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.

Abstract: A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is formed in the semiconductor substrate, along the vertical and horizontal sides of the emitter trench, has been developed. The process features forming an emitter trench in a semiconductor substrate, followed by a large angle ion implantation procedure, used to form a P type, base region, in an area of the semiconductor substrate located along the sides of the emitter trench. Formation of a polysilicon emitter structure, followed by an anneal cycle, create a narrow width, emitter region, underlying the polysilicon emitter structure, also resulting in the formation of a narrow width, P type base region, located between the overlying N type emitter region, and an underlying N type, epitaxial silicon layer.

Abstract: A method is disclosed to form memory cell structures for DRAMs in which the capacitor nodes are formed in the shape of posts that fit in an area no larger than that which is over the active regions of the semiconductor substrate. Hence, the posts are suitable to accommodate the area that is appropriate for any one of the very high density DRAMs up to and including 1 G-bit. Furthermore, one less mask is used to form the node electrode in comparison with prior art. The interior of said post structure constitutes one electrode and the exterior wall the other, while a thin dielectric separates the two polysilicon plates of the capacitor. It is shown that said post structures perform the multi-function of providing a good support during the planarization process. Optional pillars may be formed at judiciously chosen locations in the cell to provide additional storage nodes and/or more uniform support structures to more readily facilitate chemical-mechanical polishing (CMP) of the substrate surface.

Abstract: A vertical microelectronic field emitter is formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns. The trenches are filled with dielectric and the conductor layer is formed on the dielectric to form the extraction electrodes.

Abstract: A vertical microelectronic field emitter includes a conductive top portion and a resistive bottom portion in an elongated column which extends vertically from a horizontal substrate. An emitting electrode may be formed at the base of the column, and an extraction electrode may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns.

Abstract: A vertical microelectronic field emitter includes a conductive top portion and a resistive bottom portion in an elongated column which extends vertically from a horizontal substrate. An emitter electrode may be formed at the base of the column, and an extraction electrode may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips on the face of a substrate and then forming trenches in the substrate around the tips to form columns in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric and a conductor layer is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate with the trenches defining columns in the substrate. Then, tips are formed on top of the columns.

Abstract: A method of planarizing a wafer surface by using a polishing stop with chemical/mechanical polishing is described. A semiconductor wafer, on which there is a rugged surface with broad indentations, is provided. A first layer is formed over the rugged surface. A hard film layer is formed over the first layer. The first layer and the hard film layer are patterned to form polishing stop islands in the broad indentations. A second layer is formed over the rugged surface and the polishing stop islands, to create a top surface for polishing, the top surface and the rugged surface being less hard than the hard film layer. The top surface is polished in a vertical direction to remove portions of the top surface, until the top surface is co-planar with the top of the polishing stop islands. The remainder of the hard film layer is removed to complete the planar surface.

Abstract: A microelectronic field emitter includes a horizontal emitter electrode and a vertical extraction electrode on the horizontal face of a substrate. An end of the horizontal emitter electrode and the end of the vertical extraction electrode form an electron emission gap therebetween. The emitter electrode may be formed on an insulating layer which is formed on a substrate. The insulating layer also includes a sidewall, and the extraction electrode may be formed on the sidewall with one thereof extending adjacent the emitter electrode to form an electron emission gap therebetween. A vertical collector electrode may also be formed on the sidewall of a second insulating layer spaced from the first sidewall. The field emitter may be cylindrical, planar, or of various other shapes. multiple emitters, extractors and collectors may be stacked on one another.