Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: Embodiments of present invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes a MTJ stack, the MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer, wherein the free layer includes multiple sub free layers, the multiple sub free layers being multiple ferromagnetic strips placed parallel to each other on the tunnel barrier layer, the multiple ferromagnetic strips having respective first ends connected to a first electrode and respective second ends connected to a second electrode. A method of forming the MTJ structure is also provided.

Abstract: A cell activation reactor and a cell activation method are provided. The cell activation reactor includes a body, a rotating part, an upper cover, a microporous film, and multiple baffles. The body has an accommodating space, which is suitable for accommodating multiple cells and multiple magnetic beads. The rotating part is disposed in the accommodating space and includes multiple impellers. The microporous film is disposed in the accommodating space and covers multiple holes of the accommodating space. The baffles are disposed in the body. When the rotating part is driven to rotate, the interaction between the baffles and the impellers separates the cells and the magnetic beads.

Abstract: An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: A structure including alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A structure including horizontally aligned alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A method including forming alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode.

Abstract: A memory device and method of forming a projection liner under a mushroom phase change memory device with sidewall electrode process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: Memory cells and methods of forming the same include forming a hole in an interlayer dielectric to expose an end of a conductive top electrode. A phase change material is conformally deposited on surfaces of the hole. A remaining portion of the hole is filled with a dielectric material after conformally depositing the phase change material.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode. A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode, where the inner electrode and the outer electrode are on the same horizontal plane. A method including forming an inner electrode and an outer electrode simultaneously on a substrate, forming a phase change material layer above both the inner electrode and the outer electrode.

Abstract: A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.

Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

Abstract: Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: A synapse device includes a perpendicularly magnetized ferrimagnetic racetrack layer, a tunneling barrier layer disposed on the racetrack layer and a reference layer including a perpendicular magnetic alloy. The racetrack layer, the tunneling layer and the reference layer have a channel portion and contact pad portions. First and second contacts are provided over the contact pad portions, and a third contact is provided over the channel portion, wherein the first and second contacts are electrically isolated from the third contact.