Patents by Inventor Ching Wei Hsieh
Ching Wei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: 11950424Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.Type: GrantFiled: June 7, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Ting Tsai, Ching-Tzer Weng, Tsung-Hua Yang, Kao-Chao Lin, Chi-Wei Ho, Chia-Ta Hsieh
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Publication number: 20240107682Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.Type: ApplicationFiled: April 21, 2023Publication date: March 28, 2024Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20240096740Abstract: Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Wei Chiu, Chao-Wei Li, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071952Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.Type: ApplicationFiled: January 10, 2023Publication date: February 29, 2024Inventors: Chih-Chiang Tsao, Hsuan-Ting Kuo, Chao-Wei Chiu, Hsiu-Jen Lin, Ching-Hua Hsieh
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Patent number: 8564103Abstract: In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.Type: GrantFiled: March 19, 2010Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bin-Yuan Hung, Sung-Hui Huang, Wen Ting Tsai, Dian-Hau Chen, Ching Wei Hsieh
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Publication number: 20100308444Abstract: In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.Type: ApplicationFiled: March 19, 2010Publication date: December 9, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bin-Yuan Hung, Sung-Hui Huang, Wen Ting Tsai, Dian-Hau Chen, Ching Wei Hsieh