Patents by Inventor Ching-Wei Hung

Ching-Wei Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170229426
    Abstract: Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant.
    Type: Application
    Filed: September 27, 2016
    Publication date: August 10, 2017
    Inventors: Ching Wei HUNG, Wen-Jeng FAN
  • Patent number: 8159063
    Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 17, 2012
    Assignee: Powertech Technology Inc.
    Inventor: Ching-Wei Hung
  • Publication number: 20110062577
    Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.
    Type: Application
    Filed: November 4, 2009
    Publication date: March 17, 2011
    Inventor: Ching-Wei HUNG
  • Patent number: 7884472
    Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: February 8, 2011
    Assignee: Powertech Technology Inc.
    Inventors: Chin-Ti Chen, Ching-Wei Hung, Bing-Shun Yu, Chin-Fa Wang
  • Publication number: 20100147565
    Abstract: A window ball grid array substrate and its package structure includes a package substrate with a long slot arranged thereon, wherein the improvement is characterized by the long slot penetrating an end of the package substrate making the package substrate appear to be U-shaped.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Inventors: Wen-Jeng Fan, Ching-Wei Hung, Tsai-Chuan Yu
  • Publication number: 20090236739
    Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Chin-Ti CHEN, Ching-Wei HUNG, Bing-Shun YU, Chin-Fa WANG
  • Publication number: 20090236732
    Abstract: A thermal-enhanced multi-hole semiconductor package is revealed, primarily comprising a substrate with a plurality of alignment holes, a chip disposed on the substrate, an internal heat sink attached to the chip, and an encapsulant. The internal hear sink has a plurality of alignment bars and a heat dissipation surface. The alignment bars are inserted into the alignment holes, but not fully occupying the alignment holes to provide a plurality of flowing channels therein. The encapsulant completely encapsulates the alignment bars through filling the flowing channels. Therefore, the internal heat sink can be aligned to the substrate and is integrally connected with the chip and the substrate utilizing a small amount of adhesive or without any adhesive to form a composite having high rigidity and strong adhesion.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Inventors: Bing-Shun YU, Ching-Wei Hung
  • Publication number: 20090230543
    Abstract: A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat sink covering the chip, wherein the heat sink has a plurality of support portions extending from the upper surface to the lower surface of the substrate via those through holes; and a molding compound covering the chip, a portion of the substrate and the heat sink. Those support portions of the heat sink are utilized to improve the heat dissipation efficiency and the warpage issue of the package.
    Type: Application
    Filed: April 11, 2008
    Publication date: September 17, 2009
    Inventors: Ping Hsun Yu, Ching Wei Hung
  • Publication number: 20090223435
    Abstract: A substrate panel is revealed, comprising a plurality of substrate strips where each substrate strip has a plurality of substrate units and a plurality of appropriative ID marks. Each ID mark is corresponding to and formed on each substrate unit. All of the ID marks are different in a manner to simultaneously recognize both the relative locations of the substrate units to the substrate strips and the relative locations of the substrate strips to the substrate panel. In a preferred embodiment, the ID marks are disposed on exposed surfaces of the substrate units so that it is still visible after semiconductor packaging. Therefore, during or after semiconductor packaging processes, any defect found can be traced back by the ID marks on the substrate units to recognize the locations of the substrate units in the substrate panel for failure analysis to improve PCB manufacturing processes or semiconductor packaging processes for better production yields.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: Wen-Jeng FAN, Tsai-Chuan Yu, Ching-Wei Hung