Abstract: A fully-isolated metal oxide semiconductor (MOS) device includes a substrate, an isolation well, a gate structure, a source region, a gradient region, a drain region, a first well, and an electro static discharge (ESD) protection region. The isolation well is formed in the substrate, and the gate structure is formed on the isolation well. The source region and the gradient region are formed in the isolation wells on both sides of the gate structure respectively, and the drain region is formed in the gradient region. The first well is formed below the drain region in the gradient region, and the ESD protection region is formed in the first well. The isolation well and the ESD protection region have a first conductivity type, and the gradient region and the first well have a second conductivity type.

Abstract: An ESD protection circuit using GaN devices, with a ESD protection block including a first 2DEG resistor with one terminal coupled to a reference voltage, a first trigger with one terminal coupled to the another terminal of the first 2DEG resistor and with another terminal coupled to a gate of a power HEMT, a first LV-HEMT with a first gate coupled to the another terminal of the first 2DEG resistor and a first drain couple to the gate, a second 2DEG resistor with one terminal coupled to the gate, a second trigger with one terminal coupled to another terminal of the second 2DEG resistor and with another terminal coupled to the reference voltage, and a second LV-HEMT with a second gate coupled to the another terminal of the second trigger and a second drain coupled to the first source and a second source coupled to the reference voltage.

Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, a source region in the substrate, a drain region in the substrate and having a drain sidewall facing toward the source region, a gate structure on the substrate and between the drain region and the source region, and a first well in the substrate and underneath the drain region. The gate structure has a first gate sidewall facing toward the drain region. The first well has a well sidewall facing toward the source region. A first distance between the first gate sidewall and the drain sidewall is less than or equal to a second distance between the first gate sidewall and the well sidewall.

Abstract: An ESD protection circuit using GaN devices, with an ESD protection block including a first sub-block and a second sub-block. The first sub-block includes a trigger coupled to a gate of a power HEMT, a 2DEG resistor coupled to another terminal of the trigger, a LV-HEMT with a gate coupled to another terminal of the trigger and one terminal of the 2DEG resistor and with a source coupled to the gate of the power HEMT and the terminal of the trigger, and a lateral FER coupled to the gate of the LV-HEMT, the another terminal of the trigger and one terminal of the 2DEG resistor, wherein the second sub-block is provided with a device configuration completely symmetrical to the first sub-block, and corresponding devices of the two sub-blocks are coupled with each other.

Abstract: An ESD protection circuit using GaN devices, with a ESD protection block including a first 2DEG resistor with one terminal coupled to a reference voltage, a first trigger with one terminal coupled to the another terminal of the first 2DEG resistor and with another terminal coupled to a gate of a power HEMT, a first LV-HEMT with a first gate coupled to the another terminal of the first 2DEG resistor and a first drain couple to the gate, a second 2DEG resistor with one terminal coupled to the gate, a second trigger with one terminal coupled to another terminal of the second 2DEG resistor and with another terminal coupled to the reference voltage, and a second LV-HEMT with a second gate coupled to the another terminal of the second trigger and a second drain coupled to the first source and a second source coupled to the reference voltage.

Abstract: An ESD protection circuit using GaN devices, with an ESD protection block including a first sub-block and a second sub-block. The first sub-block includes a trigger coupled to a gate of a power HEMT, a 2DEG resistor coupled to another terminal of the trigger, a LV-HEMT with a gate coupled to another terminal of the trigger and one terminal of the 2DEG resistor and with a source coupled to the gate of the power HEMT and the terminal of the trigger, and a lateral FER coupled to the gate of the LV-HEMT, the another terminal of the trigger and one terminal of the 2DEG resistor, wherein the second sub-block is provided with a device configuration completely symmetrical to the first sub-block, and corresponding devices of the two sub-blocks are coupled with each other.

Abstract: An ESD protection circuit using GaN devices, with a ESD block including a first 2 DEG resistor with one terminal coupled to a gate of a power HEMT, a first trigger with one terminal coupled to another terminal of the first 2 DEG resistor and with another terminal coupled to a reference voltage, a first LV-HEMT with a first gate coupled to the another terminal of the first 2 DEG resistor and a first drain couple to the gate, a second trigger with one terminal coupled to the gate, a second 2 DEG resistor with one terminal coupled to another terminal of the second trigger and another terminal coupled to the reference voltage, and a second LV-HEMT with a second gate coupled to the another terminal of the second trigger and a second drain coupled to the first source and a second source coupled to the reference voltage.

Abstract: A fully-isolated metal oxide semiconductor (MOS) device includes a substrate, an isolation well, a gate structure, a source region, a gradient region, a drain region, a first well, and an electro static discharge (ESD) protection region. The isolation well is formed in the substrate, and the gate structure is formed on the isolation well. The source region and the gradient region are formed in the isolation wells on both sides of the gate structure respectively, and the drain region is formed in the gradient region. The first well is formed below the drain region in the gradient region, and the ESD protection region is formed in the first well. The isolation well and the ESD protection region have a first conductivity type, and the gradient region and the first well have a second conductivity type.