Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

Abstract: A device includes a semiconductor die bonded to an integrated circuit die, wherein the integrated circuit die includes a first interconnect structure that has a metal density of at least 50%, a first redistribution structure having a metal density of at least 50%, wherein the first interconnect structure is bonded to the first redistribution structure, and a composite heat dissipation material between a bottom surface of the first interconnect structure and a top surface of the first redistribution structure.

Abstract: A method includes forming integrated circuit devices on a semiconductor substrate of a wafer, forming a voltage regulator in the wafer, and forming a metal layer as a part of the wafer. A transistor is formed farther away from the semiconductor substrate than the metal layer. The transistor includes a first source/drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source/drain region to a second voltage that is lower than the first voltage, and provide the second voltage to the integrated circuit devices. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. The through via is disposed outside of and adjacent to the second semiconductor die. The through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.