Patents by Inventor Ching-Wei Tsai

Ching-Wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190067482
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Chih-Hao WANG, Wai-Yi LIEN
  • Hybrid Scheme for Improved Performance for P-type and N-type FinFETs
    Publication number: 20190067284
    Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • GATE STRUCTURE FOR SEMICONDUCTOR DEVICE
    Publication number: 20190067448
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement
    Patent number: 10211307
    Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Integrated Circuits with Gate Stacks
    Publication number: 20190035917
    Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.
    Type: Application
    Filed: November 14, 2017
    Publication date: January 31, 2019
    Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
  • Methods of Manufacturing Inner Spacers in a Gate-all-around (GAA) FET through Multi-Layer Spacer Replacement
    Publication number: 20190027570
    Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Integrated Circuit Structure and Method with Hybrid Orientation for FinFET
    Publication number: 20190006391
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 3, 2019
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190006371
    Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 3, 2019
    Inventors: Tetsu OHTOU, Ching-Wei TSAI, Kuan-Lun CHENG, Yasutoshi OKUNO, Jiun-Jia HUANG
  • FinFET semiconductor structure having hybrid substrate and method of fabricating the same
    Patent number: 10163731
    Abstract: A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Devices including gate spacer with gap or void and methods of forming the same
    Patent number: 10164069
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE ON HYBRID SUBSTRATE
    Publication number: 20180366465
    Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 20, 2018
    Inventors: Kuo-Cheng CHING, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • FinFET with a semiconductor strip as a base
    Patent number: 10157999
    Abstract: A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung, Carlos H Diaz
  • Multi-gate device and method of fabrication thereof
    Patent number: 10157799
    Abstract: A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
  • APPARATUS FOR SINGLE MOLECULAR SEQUENCING AND METHOD OF SEQUENCING NUCLEIC ACID MOLECULES
    Publication number: 20180355422
    Abstract: An apparatus suitable for single molecule sequencing. The apparatus includes at least one nanowell, a plurality of nucleic acid immobilization moieties, and a plurality of types of nucleic acid fragments. The nanowell has an observation zone. The nucleic acid immobilization moieties are disposed in or proximate to the observation zone. The nucleic acid fragments are immobilized to the nucleic acid immobilization moieties, respectively. At least one polymerase is disposed in the observation zone. A method of sequencing nucleic acid molecules using the above-mentioned apparatus is provided.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 13, 2018
    Applicant: Personal Genomics Taiwan, Inc.
    Inventors: Chung-Fan Chiou, Chao-Chi Pan, Ching-Wei Tsai, Bor-Huah Chen, Jian-Hao Ciou
  • Semiconductor device and manufacturing method thereof
    Patent number: 10115823
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Wai-Yi Lien
  • FINFET SEMICONDUCTOR STRUCTURE HAVING HYBRID SUBSTRATE AND METHOD OF FABRICATING THE SAME
    Publication number: 20180301384
    Abstract: A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 18, 2018
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Re-grown gate structure and fabrication method thereof
    Patent number: 10096597
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Chih-Hao Wang, Chung-Cheng Wu, Guo-Yung Chen, Yi-Hsiung Lin, Shang-Wen Chang, Yi-Hsun Chiu
  • Vertical device architecture
    Patent number: 10096706
    Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Jhon Jhy Liaw, Wai-Yi Lien, Jia-Chuan You, Yi-Hsun Chiu, Ching-Wei Tsai, Wei-Hao Wu
  • Method for manufacturing semiconductor structure with multi spacers
    Patent number: 10096693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • TRANSISTOR CHANNEL
    Publication number: 20180269111
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Yu-Hung CHENG, Ching-Wei TSAI, Yeur-Luen TU, Tung-I LIN, Wei-Li CHEN