Patents by Inventor Ching-Wen Cho
Ching-Wen Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6682659Abstract: A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications.Type: GrantFiled: November 8, 1999Date of Patent: January 27, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ching-Wen Cho, Kuwi-Jen Chang, Sen-Fu Chen, Kuang-Peng Lin, Shing-Jzy Tay, Szu-Hung Yang, Chai-Der Chang, Kuo-Su Huang, Jen-Shiang Leu, Weng-Liang Fang, Jyh-Ping Wang, Jow-Feng Lee
-
Patent number: 6660624Abstract: A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and heating the process surface according to a temperature profile to reduce a fluorine contamination level.Type: GrantFiled: February 14, 2002Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiann-Tyng Tzeng, Jih-Ren Tsai, Michael Wu, Ching-Wen Cho
-
Patent number: 6627475Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region. A field oxide isolation region is then formed which extends beyond the p-type region and also covers the p-type region except for an active region and an overlap part of the n-type photodiode region. An n-channel MOSFET is fabricated in the active region with one of the source/drain regions of the MOSFET extending over the overlap part of the n-type photodiode region. A blanket transparent insulating layer is then deposited.Type: GrantFiled: January 18, 2000Date of Patent: September 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hua Yu Yang, Ching-Wen Cho, Chih-Heng Shen
-
Patent number: 6624466Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.Type: GrantFiled: February 12, 2002Date of Patent: September 23, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Sen-Fu Chen, Ching-Wen Cho, Huan-Wen Wang, Chih-Heng Shen
-
Patent number: 6620683Abstract: A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.Type: GrantFiled: December 4, 2001Date of Patent: September 16, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Boson Lin, Ching-Wen Cho, David Ho
-
Publication number: 20030153196Abstract: A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and heating the process surface according to a temperature profile to reduce a fluorine contamination level.Type: ApplicationFiled: February 14, 2002Publication date: August 14, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiann-Tyng Tzeng, Jih-Ren Tsai, Michael Wu, Ching-Wen Cho
-
Publication number: 20020110972Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.Type: ApplicationFiled: February 12, 2002Publication date: August 15, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Sen-Fu Chen, Ching-Wen Cho, Huan-Wen Wang, Chih-Heng Shen
-
Patent number: 6380030Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.Type: GrantFiled: April 23, 1999Date of Patent: April 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Sen-Fu Chen, Ching-Wen Cho, Huan-Wen Wang, Chih-Heng Shen
-
Patent number: 6157867Abstract: A method for operating a plasma processing system comprises the following steps. Produce a plasma in a plasma processing chamber operating upon a selected workpiece. Perform in situ detection of electromagnetic radiation of a certain wavelength generated in the plasma in the plasma processing chamber. Calculate a first intensity difference of the certain wavelength from a set point of intensity. Halt production of the plasma in the plasma processing chamber if the first intensity difference is outside of specifications.Type: GrantFiled: February 27, 1998Date of Patent: December 5, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yuan-Ko Hwang, Ching-Wen Cho
-
Patent number: 6077776Abstract: A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.Type: GrantFiled: March 18, 1998Date of Patent: June 20, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ching-Wen Cho, Cheng-Fu Hsu, Sen-Fu Chen, Po-Tao Chu
-
Patent number: 6071826Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.Type: GrantFiled: February 12, 1999Date of Patent: June 6, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ching-Wen Cho, Hua-Yu Yang, Sen-Fu Chen, Chih-Heng Shen, Wen-Cheng Chien, Chang-Jen Wu, Chi-Hsin Lo, Hui-Chen Chu
-
Patent number: 6006764Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.Type: GrantFiled: January 28, 1997Date of Patent: December 28, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Tao Chu, Ching-Wen Cho, Chia-Hung Lai, Chih-Chien Hung