Patents by Inventor Ching-Wen Hsue

Ching-Wen Hsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9419324
    Abstract: A basic cell of a microwave group delay line is disclosed for tuning the electromagnetic signal propagation delay time from signal source (1) to output (5), wherein two pairs of unequal-length stubs ((L1b, L1b), (L2b, L2b)) are placed on both sides of the main transmission path (2) in the signal layer and two pairs of complementary slot-lines ((L1t, L1t), (L2t, L2t)) are placed on both sides of the main transmission path (2) in ground plane for microstrip structure. Unequal-length stubs are placed in central layer and complementary slot-lines are placed in either outer conductor ground planes for strip-line structure. The characteristic impedances (Z0, 2Z1b, 2Z2b, 2Z1t, 2Z2t) of transmission paths are selected to control group delay time and minimize reflection of signals from signal source to output. A cascade connection of the basic cell forms a delay line system.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: August 16, 2016
    Inventors: Ching-Wen Hsue, Thomas Hsue
  • Publication number: 20150200438
    Abstract: A basic cell of a microwave group delay line is disclosed for tuning the electromagnetic signal propagation delay time from signal source (1) to output (5), wherein two pairs of unequal-length stubs ((L1b, L1b), (L2b, L2b)) are placed on both sides of the main transmission path (2) in the signal layer and two pairs of complementary slot-lines ((L1t, L1t), (L2t, L2t)) are placed on both sides of the main transmission path (2) in ground plane for microstrip structure. Unequal-length stubs are placed in central layer and complementary slot-lines are placed in either outer conductor ground planes for strip-line structure. The characteristic impedances (Z0, 2Z1b, 2Z2b, 2Z1t, 2Z2t) of transmission paths are selected to control group delay time and minimize reflection of signals from signal source to output. A cascade connection of the basic cell forms a delay line system.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Inventors: Ching-Wen HSUE, Thomas HSUE
  • Patent number: 8624790
    Abstract: The present invention relates to a porous magnetic antenna, comprising: an antenna; an insulating layer, having one side next to said antenna; and a magnetic layer, placed next to the other side of the insulating layer, separated from said antenna with a distance, and having at least one hole. The porous magnetic antenna has the advantages of shaping the field pattern, lowering the sensitivity, improving the gain value and possessing stable directionality.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 7, 2014
    Assignee: Mingchi University of Technology
    Inventors: Wen-Cheng Lai, Ching-Wen Hsue, Li-Ming Lo
  • Publication number: 20110006962
    Abstract: The present invention relates to a porous magnetic antenna, comprising: an antenna; an insulating layer, having one side next to said antenna; and a magnetic layer, placed next to the other side of the insulating layer, separated from said antenna with a distance, and having at least one hole. The porous magnetic antenna has the advantages of shaping the field pattern, lowering the sensitivity, improving the gain value and possessing stable directionality.
    Type: Application
    Filed: January 19, 2010
    Publication date: January 13, 2011
    Inventors: Wen-Cheng Lai, Ching-Wen Hsue, Li-Ming Lo
  • Publication number: 20100245199
    Abstract: A magnetic antenna is provided. The magnetic antenna includes an antenna; and a magnetic piece configured near the antenna with a distance therebetween.
    Type: Application
    Filed: July 1, 2009
    Publication date: September 30, 2010
    Inventors: Wen-Cheng LAI, Ching-Wen Hsue, Li-Ming Lo
  • Patent number: 5392293
    Abstract: A current sensor (10), for sensing a quiescent current (I.sub.DDQ) drawn by an integrated circuit (12) from a supply voltage V.sub.DD includes a current sink and voltage transducer (14) for sinking current from the integrated circuit during a logic transition and for providing a voltage indicative of the quiescent current when the circuit operates in its quiescent state. A comparator (18) compares this voltage to a reference voltage representative of a prescribed quiescent current. The comparator is coupled to a preamplifier stage (38) which serves to generate an indicating voltage in accordance with the comparator output signal. The indicating voltage from the preamplifier stage is stabilized by a stabilizing circuit (58) against variations in the supply voltage V.sub.DD to assure that the indicating voltage provides an accurate measure of whether the quiescent current I.sub.DDQ is above or below a prescribed current.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: February 21, 1995
    Assignee: AT&T Corp.
    Inventor: Ching-Wen Hsue
  • Patent number: 4877971
    Abstract: A network is disclosed for distributing a signal from a single source (18) to each of 2.sup.n (20.sub.1, 20.sub.2 . . . 20.sub.2n where n is an integer, such that the signals supplied to the loads each have substantially the same phase and amplitude. The network comprises 2.sup.n paths (22.sub.1, 22.sub.2 . . . 22.sub.2n), each coupling the source to a separate one of the loads. Each path is comprised of 2n+1 serially coupled segments 24.sub.1, 24.sub.4 . . . 24.sub.2n+1) with 2n-1 of the segments (24.sub.1, 24.sub.4 . . . 24.sub.2n-1) of each branch being common to another path. The segments in each path have corresponding impedances (Z.sub.1, Z.sub.2 . . . Z.sub.2n+1), respectively, which are selected so that each load is substantially matched to the source and that the internal reflection of the signals within each path is minimized.
    Type: Grant
    Filed: August 31, 1988
    Date of Patent: October 31, 1989
    Assignee: American Telephone and Telegraph Company
    Inventor: Ching-Wen Hsue
  • Patent number: 4841240
    Abstract: A determination of whether each of a pair of interconnected nodes (22) on a circuit board (12) is connected to a corresponding one of a pair of nodes (28) on a translator board (14) via a test fixture pin (18) is had by coupling one of the translator board nodes to circuit ground. The other of the pair of nodes on the translator board is coupled to the gate of a field effect transistor (FET) (34) whose gate-to-source portion is shunted by a capacitor (38). The drain-to-source portion of the FET (34) is coupled in series with a resistor (36) between circuit ground and a voltage source supplying a potential below ground potential. When continuity exists between each of the pair of nodes (22 and 28) and each of the pair of pins (18), the FET(34) conducts, causing the voltage across the resistor (36) to change. By monitoring the voltage across the resistor (36), an indication can be had as to whether continuity exists.
    Type: Grant
    Filed: January 29, 1988
    Date of Patent: June 20, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Ching-Wen Hsue, Wha-Joon Lee