Abstract: The present disclosure provides a method and apparatus for driving a display panel, and a display device. The method includes: upon driving an ith row of sub-pixels, scanning a gate line connected to a jth row of sub-pixels, and determining a reference grayscale of each of the jth row of sub-pixels in each candidate connection mode, wherein a plurality of data lines have a plurality of candidate connection modes; determining a target connection mode that minimizes a grayscale variation degree of the jth row of sub-pixels from the plurality of candidate connection modes; connecting the plurality of data lines according to the target connection mode; and disconnecting the plurality of data lines before driving the jth row of sub-pixels through the plurality of data lines.

Abstract: The present disclosure provides a method and apparatus for driving a display panel, and a display device. The method includes: upon driving an ith row of sub-pixels, scanning a gate line connected to a jth row of sub-pixels, and determining a reference grayscale of each of the jth row of sub-pixels in each candidate connection mode, wherein a plurality of data lines have a plurality of candidate connection modes; determining a target connection mode that minimizes a grayscale variation degree of the jth row of sub-pixels from the plurality of candidate connection modes; connecting the plurality of data lines according to the target connection mode; and disconnecting the plurality of data lines before driving the jth row of sub-pixels through the plurality of data lines.

Abstract: A display apparatus, and a display controller and an operating method thereof are provided. The display controller includes a controller, a buffer, and a compression/decompression unit. The controller receives an original frame from a host. The controller controls a display module to display the original frame provided by the host in a non-still frame mode. The compression/decompression unit is coupled between the buffer and the controller. The controller compresses the original frame to the buffer through the compression/decompression unit. If the controller operates in a still frame mode, the controller decompresses a compressed frame in the buffer to obtain a decompressed frame through the compression/decompression unit, and controls the display module to display the decompressed frame.

Abstract: An output enable signal transformation device for a gate driver in an LCD device includes a reception terminal coupled to a timing generator of the LCD device for receiving an enable synchronization signal, an enable clock signal and a plurality of enable control signals generated by the timing generator, a shift register module coupled to the reception terminal for shifting the enable synchronization signal according to the enable clock signal, a multiplexer module coupled to the shift register module and the timing generator for generating a plurality of output enable signals according to the enable synchronization signal and the plurality of enable control signals, and an output terminal coupled to the multiplexer module and a logic circuit of the gate driver for outputting the plurality of output enable signals to the logic circuit.

Abstract: An output enable signal transformation device for a gate driver in an LCD device includes a reception terminal coupled to a timing generator of the LCD device for receiving an enable synchronization signal, an enable clock signal and a plurality of enable control signals generated by the timing generator, a shift register module coupled to the reception terminal for shifting the enable synchronization signal according to the enable clock signal, a multiplexer module coupled to the shift register module and the timing generator for generating a plurality of output enable signals according to the enable synchronization signal and the plurality of enable control signals, and an output terminal coupled to the multiplexer module and a logic circuit of the gate driver for outputting the plurality of output enable signals to the logic circuit.