Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A network equipment monitoring analysis aid and guidance method, and its terminal device and readable storage medium are disclosed. The method is loaded into an equipment to execute the steps of collecting a history total traffic of a terminal device connected to the equipment; capturing a history time period traffic of each time period of the terminal device; analyzing the history total traffic and the history time period traffic by a quantitative analysis to generate a quantitative information of the terminal device; and presenting a corresponding guide information on a user interface according to the quantitative information. The guide information can be used to clearly mark a network traffic level of each terminal device in each time period and present it in a user interface, so as to visually present a network user's network activity behavior, guide parental use and monitoring, and set guidelines for members.

Abstract: A network equipment monitoring analysis aid and guidance method, and its terminal device and readable storage medium are disclosed. The method is loaded into an equipment to execute the steps of collecting a history total traffic of a terminal device connected to the equipment; capturing a history time period traffic of each time period of the terminal device; analyzing the history total traffic and the history time period traffic by a quantitative analysis to generate a quantitative information of the terminal device; and presenting a corresponding guide information on a user interface according to the quantitative information. The guide information can be used to clearly mark a network traffic level of each terminal device in each time period and present it in a user interface, so as to visually present a network user's network activity behavior, guide parental use and monitoring, and set guidelines for members.

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract: A computerized carbon footprint inventory method of carrying out a carbon footprint inventory of a product is implemented in a computing device. The computing device receives an inventory procedure selected by a user, sets products as inventory targets, loads data as to materials in the product, and determines which materials are to be inventoried according to a weight analysis and according to a carbon dioxide equivalent (CO2e) analysis. The computing device further receives an inventory list uploaded by a vendor, sets a calculation boundary of the carbon footprint inventory and a priority of the material, calculates any uncertainties in relation to the product and the CO2e of the product, generates an inventory report including the uncertainties and the CO2e of the product, and executes an internal verification and an external verification of the inventory report.

Abstract: A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.

Abstract: A high speed memory system includes a plurality of memory devices; a plurality of buffers; and a memory controller. The plurality of buffers is respectively coupled to the plurality of memory devices. The memory controller is coupled to the plurality of buffers, for generating a plurality of control signal to the plurality of buffers and sequentially controlling access to the plurality of memory devices in a time-sharing manner according to a clock.

Abstract: A memory architecture of a display device including a display data memory block and a processor is provided. The display data memory block includes N sub-memories and N arbiters respectfully coupled to the N sub-memories, wherein N is a positive integer larger than 1. The processor is used for respectfully and continuously outputting corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectfully output the corresponding address signals to corresponding sub-memories, such that the N sub-memories simultaneously access data respectfully according to the N address signals.

Abstract: A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory.

Abstract: When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.

Abstract: When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.