Patents by Inventor Ching-Wen Lu

Ching-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155231
    Abstract: A method for performing light shaping with aid of an adaptive projector and associated apparatus are provided.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Wu-Feng Chen, Ching-Wen Wang, Cheng-Che Tsai, Hsueh-Tsung Lu
  • Patent number: 11979661
    Abstract: A method for performing light shaping with aid of an adaptive projector and associated apparatus are provided.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: May 7, 2024
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Wu-Feng Chen, Ching-Wen Wang, Cheng-Che Tsai, Hsueh-Tsung Lu
  • Publication number: 20240119613
    Abstract: A structured-light three-dimensional (3D) scanning system includes a projector that emits a projected light with a predetermined pattern onto an object; an image capture device that generates a captured image according to a reflected light reflected from the object, the predetermined pattern of the projected light being distorted due to 3D shape of the object, thereby resulting in a distorted pattern; a depth decoder that converts the distorted pattern into a depth map representing the 3D shape of the object; and a depth fusion device that generates a fused depth map according to at least two different depth maps associated with the object.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Hsueh-Tsung Lu, Ching-Wen Wang, Cheng-Che Tsai, Wu-Feng Chen
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240085172
    Abstract: The device includes a projecting device, an image sensor and a computing circuit. The projecting device provides a light beam having a predetermined pattern that is projected onto an object. The image sensor receives the light beam reflected from the object to generate an image. The computing circuit compares the image with a first ground-truth image and a ground-truth image to generate a first depth value and a second depth value respectively. The first and second depth values are combined to generate a depth result.
    Type: Application
    Filed: September 11, 2022
    Publication date: March 14, 2024
    Inventors: Wu-Feng CHEN, Ching-Wen WANG, Cheng Che TSAI, Hsueh-Tsung LU
  • Publication number: 20050263891
    Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: April 7, 2005
    Publication date: December 1, 2005
    Inventors: Bih-Huey Lee, Hong-Yuan Chu, Ping-Kun Wu, Ching-Wen Lu, Jing-Cheng Lin, Shau-Lin Shue, Shing-Chyang Pan