Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.

Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.

Abstract: A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.

Abstract: A method for calculating a feed forward equalizer coefficient of a feed forward equalizer in a minimum mean square error decision feedback equalizer (MMSE-DFE) based on a fast transversal recursive least squares (FT-RLS) algorithm is provided. The length of the feed-forward equalizer is LF, which is a positive integer. The method includes an outer iteration having an LF number of iterations. The outer iteration includes an inner iteration having an n number of iterations, where n is an integer between 0 and (LF?2).

Abstract: A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an indecipherable signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the indecipherable signal to generate an encrypted message.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.

Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.

Abstract: An automatic gain control system with hysteresis switching includes an error calculator for calculating the difference between a first estimation signal and a take over point (TOP) value to produce an error signal. A hysteresis comparator compares the first estimation signal and the TOP value to produce a control signal. A first gain control loop generates a first gain control signal based on the control signal to control a gain of a first variable gain amplifier. A second gain control loop generates a second gain control signal based on the control signal to control a gain of a second variable gain amplifier. As the first estimation signal leaves a hysteresis region of the hysteresis comparator, the first gain control signal is monotonically decreasing and the first gain control signal is monotonically increasing. As a result, the total gain is stable.

Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Abstract: A circuit for generating a tracking error signal is provided. The circuit includes a digitized circuit, a short signal removing circuit and phase comparator. The digitized circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals.

Abstract: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.

Abstract: An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.

Abstract: A timing recovery apparatus and method with frequency protection are provided. The apparatus uses a frequency estimator to calculate and store an estimated frequency value as a pre-stored estimated frequency value when timing quality is good. A defect detector is used to determine whether a defective portion on a disk medium has been detected. When a defective portion has been detected, the pre-stored estimated frequency value is then used as the basis of phase lock and frequency lock to generate a reference clock. As the read operation performed over the defective portion is finished, the normal frequency lock mechanism is restarted. At this moment, the frequency lock mechanism can take less time to lock the input signal. Thus, the invention significantly reduces the missing readable data due to loss of frequency lock, and never breaks the normal tracking-frequency operation of the frequency lock mechanism.

Abstract: A communications system providing SDMA communication channels in a non-SDMA (non-spatial division multiple access) system and used in a specific area to establish wireless communications with mobile stations in the area comprises a smart antenna to establish wireless communications with the mobile stations, a base station controller managing transmissions and receiving information between every mobile station and an outgoing communications network, a plurality of base transceiver stations electrically connected with the base station controller, each of them establishing the wireless communications between the mobile stations and the base station controller, and a spatial spectrum management system connected between the smart antenna and the base transceiver stations.

Abstract: A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.

Abstract: An investment molding flask assembly having a base with a central positioning boss protruded from a center thereof and at least one positioning annular groove defined therein around the central positioning boss, and a conical sleeve formed with a small opening end to be securely positioned on the base without any displacement in horizontal directions by means of the central positioning boss or the positioning annular groove. Whereby, the conical sleeve can be readily removable from a solidified semi-finished investment mold, and then the solidified semi-finished investment mold is sent into an oven independently for heating. Therefore the sleeve can be used repeatedly, and the investment mold can be manufactured rapidly and readily.