Patents by Inventor Ching-Yang Wen
Ching-Yang Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220013430Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
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Publication number: 20210313116Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.Type: ApplicationFiled: April 21, 2020Publication date: October 7, 2021Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN, CHAO JIN
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Publication number: 20210125921Abstract: A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.Type: ApplicationFiled: January 4, 2021Publication date: April 29, 2021Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
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Publication number: 20210104602Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: United Microelectronics Corp.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Publication number: 20210098624Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.Type: ApplicationFiled: December 9, 2020Publication date: April 1, 2021Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
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Patent number: 10923599Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.Type: GrantFiled: May 9, 2019Date of Patent: February 16, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
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Patent number: 10903314Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: GrantFiled: June 25, 2018Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Publication number: 20200328311Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.Type: ApplicationFiled: May 9, 2019Publication date: October 15, 2020Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
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Patent number: 10763170Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.Type: GrantFiled: March 22, 2018Date of Patent: September 1, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Purakh Raj Verma, Su Xing, Ching-Yang Wen
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Publication number: 20200075514Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.Type: ApplicationFiled: September 27, 2018Publication date: March 5, 2020Inventors: Purakh Raj Verma, Wen-Shen Li, Ching-Yang Wen
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Publication number: 20190355812Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: ApplicationFiled: June 25, 2018Publication date: November 21, 2019Applicant: United Microelectronics Corp.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Publication number: 20190252253Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.Type: ApplicationFiled: March 22, 2018Publication date: August 15, 2019Inventors: Purakh Raj Verma, Su Xing, Ching-Yang Wen
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Publication number: 20190051666Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.Type: ApplicationFiled: August 31, 2017Publication date: February 14, 2019Inventors: Wen-Shen Li, XIAOYUAN ZHI, XINGXING CHEN, Ching-Yang Wen
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Publication number: 20080200039Abstract: The invention is directed to a nitridation process for a wafer. The nitridation process comprises steps of disposing the wafer on a top surface of a chuck in a nitridation process tool, wherein a plurality of concentric pipe coils is disposed close to the bottom surface of the chuck. Then, the chuck is heated and the chuck is regionally cooling down by applying a coolant into the concentric pipe coils, wherein the flow rates of the coolant in the concentric pipe coils are different from each other. Furthermore, a plasma nitridation process is performed on the wafer.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wenshen Li, Chien-Kee Pang, Ching-Yang Wen, Teng-Ming Hoong