Patents by Inventor Ching-Yao Lin

Ching-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288029
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Patent number: 11112322
    Abstract: A bicycle has a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 7, 2021
    Assignee: GIANT MANUFACTURING CO. LTD.
    Inventors: Chih-Kai Chang, Ching-Yao Lin
  • Patent number: 11031376
    Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
  • Patent number: 10985115
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20210048360
    Abstract: A bicycle capable of measuring power is disclosed. The bicycle comprises a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Applicant: Giant Manufacturing Co. Ltd.
    Inventors: CHIH-KAI CHANG, CHING-YAO LIN
  • Publication number: 20210046992
    Abstract: A bicycle capable of measuring power is disclosed. The bicycle comprises a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Application
    Filed: May 13, 2020
    Publication date: February 18, 2021
    Applicant: Giant Manufacturing Co. Ltd.
    Inventors: Chih-Kai CHANG, Ching-Yao LIN, Chung-Wei LIN
  • Publication number: 20210020607
    Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
  • Publication number: 20200402927
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10867953
    Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ai-Tee Ang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin
  • Publication number: 20200321290
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10797008
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10734328
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20200118945
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a die attach material disposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure. A first shortest distance from a midpoint of a bottom edge of the semiconductor die to a midpoint of an bottom edge of an extruded region of the die attach material in a width direction of the semiconductor die is greater than a second shortest distance between an endpoint of the bottom edge of the semiconductor die to an endpoint of the bottom edge of the extruded region of the die attach material. The insulating encapsulant encapsulates the semiconductor die and the die attach material. An inclined interface is between the insulating encapsulant and the extruded region of the die attach material.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20200091091
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A dielectric layer is formed on a conductive pattern and in a space between the conductive pattern, where a concave area of the dielectric layer is formed corresponding to the space between the conductive pattern. A semiconductor die is disposed on the concave area of the dielectric layer with a die attach material interposed therebetween. A pressure is applied to the die attach material so that the concave area of the dielectric layer is filled with the die attach material, and a portion of the die attach material is extruded from the concave area to expand wider than an area of the semiconductor die. An insulating encapsulant is formed on the dielectric layer to cover the semiconductor die. Other methods for forming a semiconductor package are also provided.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10510686
    Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20190358996
    Abstract: A reinforced prepreg which is applied to a wear-resistant layer structure of a braking track is provided. The reinforced prepreg includes a fiber fabric and a mixture mixed with the fiber fabric. The mixture includes a resin and a plurality of needle-shaped crystals having microscale or nanoscale sizes mixed with the resin.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 28, 2019
    Inventors: Chih-Kai CHANG, Yao-Tun CHIANG, Ching-Yao LIN
  • Publication number: 20190333869
    Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20190252339
    Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ai-Tee Ang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin
  • Publication number: 20190240928
    Abstract: A method for forming a resin-based composite structure is provided. The method includes: providing a prepreg layup, wherein the prepreg layup includes an epoxy resin-carbon fiber composite material; covering a thermal-fusion material on a surface of the prepreg layup; and performing a molding and curing process to fuse the thermal-fusion material with the prepreg layup. Wherein the molding and curing process includes: heating at a first temperature to melt, soften and fully fuse the thermal-fusion material with the prepreg layup; and heating at a second temperature to solidify the thermal-fusion material for forming the resin-based composite structure. Wherein the first temperature is lower than the second temperature.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 8, 2019
    Inventors: Yao-Tun CHIANG, Chih-Kai CHANG, Ching-Yao LIN
  • Publication number: 20190201736
    Abstract: A crank apparatus includes a crank arm having at least one cavity on one of the surfaces of the crank arm, at least one thin material layer embedded within the at least one cavity and having an exposed outer surface, and at least one sensing element attached to the outer surface of the thin material layer. The crank arm is manufactured of a material with non-uniform strain characteristics, the thin material layer is manufactured of a material with uniform strain characteristics, the crank arm is adapted to be deformed by a force, the thin material layer is adapted to be deformed correspondingly with the deformation of the crank arm, the at least one sensing element is adapted to measure the corresponding strain of the thin material layer to measure the force applied on the crank arm. A bicycle and a stationary exercise bicycle equipped with the crank apparatus are further provided.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Applicant: Giant Manufacturing Co., Ltd.
    Inventors: Chung-Wei Lin, Hsaio-Wen Hsu, Chih-Hsiang Shen, Ching-Yao Lin