Patents by Inventor Ching-Yao Lin

Ching-Yao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278547
    Abstract: A self-powered apparatus is used for various kinds of cycling and indoor exercise devices. The self-powered apparatus includes a pedal unit, a spindle, a generator and an energy storage element. The pedal unit includes an inner surface to form an accommodating space therein. The spindle is accommodated in the accommodating space. The generator includes a stator and a rotor. The stator is disposed on the spindle, the rotor is disposed on the inner surface of the pedal unit, and the rotor surrounds the stator correspondingly and is non-contact with the stator. The energy storage element is electrically coupled to the generator. When the pedal unit is being pedaled to rotate by a rider, the stator is fixed on the spindle, the rotor rotates relatively to the stator and along with the pedal unit, and a power is generated by the generator to charge the energy storage element.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: April 15, 2025
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Ching-Yao Lin, Hsiao-Wen Hsu, Chin-Lai Huang
  • Publication number: 20230317585
    Abstract: A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Wei-Jhan Tsai, Sheng-Feng Weng, Ching-Yao Lin, Ming-Yu Yen, Kai-Fung Chang, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230174185
    Abstract: A power-measuring device includes a spindle, a power gauge, an electrical circuit, and a cover. The spindle is configured to provide a coupling with a driving unit. The spindle includes a battery chamber within a hollow space of the spindle. The battery chamber is configured to receive a battery unit. The power gauge is coupled with the spindle to measure power applied to the spindle for driving a movement of the driving unit. The electrical circuit is coupled with the spindle, and electrically coupled with the power gauge. The electrical circuit is coupled with the battery unit and configured to receive and process signals from the power gauge. The cover is coupled with the spindle and arranged to enclose at least a portion of at least one of the power gauge and the electrical circuit.
    Type: Application
    Filed: November 24, 2022
    Publication date: June 8, 2023
    Applicant: GIANT MANUFACTURING CO., LTD.
    Inventors: Ching-Yao LIN, Chin-Lai HUANG, Chih-Kai CHANG, Chung-Wei LIN
  • Publication number: 20230154764
    Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.
    Type: Application
    Filed: March 21, 2022
    Publication date: May 18, 2023
    Inventors: Tzu-Sung Huang, Tsung-Hsien Chiang, Ming Hung Tseng, Hao-Yi Tsai, Yu-Hsiang Hu, Chih-Wei Lin, Lipu Kris Chuang, Wei Lun Tsai, Kai-Ming Chiang, Ching Yao Lin, Chao-Wei Li, Ching-Hua Hsieh
  • Publication number: 20230019925
    Abstract: A self-powered apparatus is used for various kinds of cycling and indoor exercise devices. The self-powered apparatus includes a pedal unit, a spindle, a generator and an energy storage element. The pedal unit includes an inner surface to form an accommodating space therein. The spindle is accommodated in the accommodating space. The generator includes a stator and a rotor. The stator is disposed on the spindle, the rotor is disposed on the inner surface of the pedal unit, and the rotor surrounds the stator correspondingly and is non-contact with the stator. The energy storage element is electrically coupled to the generator. When the pedal unit is being pedaled to rotate by a rider, the stator is fixed on the spindle, the rotor rotates relatively to the stator and along with the pedal unit, and a power is generated by the generator to charge the energy storage element.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 19, 2023
    Inventors: Ching-Yao LIN, Hsiao-Wen HSU, Chin-Lai HUANG
  • Patent number: 11541687
    Abstract: A reinforced prepreg which is applied to a wear-resistant layer structure of a braking track is provided. The reinforced prepreg includes a fiber fabric and a mixture mixed with the fiber fabric. The mixture includes a resin and a plurality of needle-shaped crystals having microscale or nanoscale sizes mixed with the resin.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 3, 2023
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Chih-Kai Chang, Yao-Tun Chiang, Ching-Yao Lin
  • Patent number: 11508671
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 11364690
    Abstract: A method for forming a resin-based composite structure is provided. The method includes: providing a prepreg layup, wherein the prepreg layup includes an epoxy resin-carbon fiber composite material; covering a thermal-fusion material on a surface of the prepreg layup; and performing a molding and curing process to fuse the thermal-fusion material with the prepreg layup. Wherein the molding and curing process includes: heating at a first temperature to melt, soften and fully fuse the thermal-fusion material with the prepreg layup; and heating at a second temperature to solidify the thermal-fusion material for forming the resin-based composite structure. Wherein the first temperature is lower than the second temperature.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 21, 2022
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Yao-Tun Chiang, Chih-Kai Chang, Ching-Yao Lin
  • Patent number: 11292544
    Abstract: A bicycle has a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: April 5, 2022
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Chih-Kai Chang, Ching-Yao Lin, Chung-Wei Lin
  • Publication number: 20220036151
    Abstract: The present invention discloses a system for finding shortest pathways between neurons in a neuronal network, including a neuronal space generating device for establishing a three-dimensional or higher dimensional neuronal space database (which may be neuron image database), wherein the three dimensional or higher dimensional neuronal space database includes a plurality of neurons distributed therein. A neurons connection determining device is used for determined whether there is a connection between each of the plurality of neurons in the three-dimensional or higher dimensional neuronal space database and the others of the plurality of neurons in the three-dimensional or higher dimensional neuronal space database. A neuronal shortest pathway tables generating device is used for calculating a shortest pathway table of all of a plurality of connected neurons and then stored in a storage device.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Inventors: Ann-Shyn Chiang, Ching-Yao Lin, Hsiu-Ming Chang, Kuen-Long Tsai, Chang-Huain Hsieh
  • Patent number: 11135474
    Abstract: A crank apparatus includes a crank arm having at least one cavity on one of the surfaces of the crank arm, at least one thin material layer embedded within the at least one cavity and having an exposed outer surface, and at least one sensing element attached to the outer surface of the thin material layer. The crank arm is manufactured of a material with non-uniform strain characteristics, the thin material layer is manufactured of a material with uniform strain characteristics, the crank arm is adapted to be deformed by a force, the thin material layer is adapted to be deformed correspondingly with the deformation of the crank arm, the at least one sensing element is adapted to measure the corresponding strain of the thin material layer to measure the force applied on the crank arm. A bicycle and a stationary exercise bicycle equipped with the crank apparatus are further provided.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 5, 2021
    Assignee: Giant Manufacturing Co., Ltd.
    Inventors: Chung-Wei Lin, Hsaio-Wen Hsu, Chih-Hsiang Shen, Ching-Yao Lin
  • Patent number: 11112322
    Abstract: A bicycle has a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 7, 2021
    Assignee: GIANT MANUFACTURING CO. LTD.
    Inventors: Chih-Kai Chang, Ching-Yao Lin
  • Patent number: 11031376
    Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
  • Patent number: 10985115
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20210046992
    Abstract: A bicycle capable of measuring power is disclosed. The bicycle comprises a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Application
    Filed: May 13, 2020
    Publication date: February 18, 2021
    Applicant: Giant Manufacturing Co. Ltd.
    Inventors: Chih-Kai CHANG, Ching-Yao LIN, Chung-Wei LIN
  • Publication number: 20210048360
    Abstract: A bicycle capable of measuring power is disclosed. The bicycle comprises a spider including a torque input section and at least one torque output section; a crank assembly coupled with the spider through the torque input section and applying an input torque to the spider; a chainring mounted to the spider through the at least one torque output section and receiving an output torque from the spider; a gauge disposed and oriented generally along a tangential direction or a quasi-tangential direction with respect to the torque input section and the at least one torque output section; and a circuitry coupled to the gauge and receiving a signal from the gauge.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Applicant: Giant Manufacturing Co. Ltd.
    Inventors: CHIH-KAI CHANG, CHING-YAO LIN
  • Publication number: 20210020607
    Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
  • Publication number: 20200402927
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10867953
    Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ai-Tee Ang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin
  • Publication number: 20200321290
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang