Patents by Inventor Ching-Yi Hsu

Ching-Yi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105546
    Abstract: An electrical connector is configured to be assembled with a joint. The electrical connector includes an outer casing, a seat body and a plurality of insulation-displacement contacts. The outer casing includes a first casing and a second casing. The first casing includes an accommodation portion, a threaded portion and a connection portion, the accommodation portion and the threaded portion are integrally connected to each other via the connection portion. The accommodation portion is configured to be assembled with the joint, the threaded portion and the second casing are screwed with each other, and the first casing and the second casing together form an accommodation space. The seat body is disposed in the accommodation space. The insulation-displacement contacts are fixed to the seat body and extend to the accommodation portion.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 27, 2025
    Applicant: TELEBOX INDUSTRIES CORP.
    Inventors: Ching-Yi HSU, Hung Yu WU
  • Publication number: 20240379841
    Abstract: A semiconductor device includes a first well region having the first conductivity type and a second well region having the second conductivity type formed in a substrate having the first conductivity type. An isolation component and a third well region are formed in the second well region. The third well region has the first conductivity type and is in contact with the bottom surface of the isolation component. A first doping region is formed in the first well region and a second doping region is formed in the second well region. The first and second doping regions have the second conductivity type and are disposed at opposite sides of the gate structure. The interface between the first well region and the second well region is positioned between the isolation component and the first doping region. The interface is separated from the third well region by a lateral distance.
    Type: Application
    Filed: May 8, 2023
    Publication date: November 14, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Po-Hao CHIU, Nai-Lun CHENG, Pi-Kuang CHUANG, Chih-Hung LIN, Ching-Yi HSU
  • Publication number: 20240128313
    Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
  • Publication number: 20230387103
    Abstract: A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsien-Feng LIAO, Jian-Hsing LEE, Chieh-Yao CHUANG, Ting-Yu CHANG, Yeh-Ning JOU, Shao-Chang HUANG, Kan-Sen CHEN, Nai-Lun CHENG, Ching-Yi HSU, Yu-Chen WU
  • Publication number: 20230307268
    Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yung-Hsiang Chen, Yun-Chou Wei, Ke-Fang Hsu, Ching-Yi Hsu, Yen-Shih Ho
  • Patent number: 11436992
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 6, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung Chin, Ching-Yi Hsu, Chang-He Liu, Chih-Cherng Liao, Jun-Wei Chen, Leuh Fang
  • Patent number: 11387361
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
  • Patent number: 11158533
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi Hsu, Pi-Kuang Chuang, Po-Sheng Hu
  • Publication number: 20210249536
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu HUANG, Tse-Hsiao LIU, Pao-Hao CHIU, Chih-Cherng LIAO, Ching-Yi HSU
  • Patent number: 10984704
    Abstract: A display device is provided. The display device includes a data signal transmitter and a display panel. The data signal transmitter is used to transmit data signals. A display area of the display panel is divided into sub-display areas. Each sub-display area includes light emitting diodes, a data line, column switches, and row switches. A portion of the data line is formed as a data induction coil to receive one of the data signals by wireless sensing. The display panel selects one of the light emitting diodes as a selected light emitting diode by the column switches and the row switches. The selected light emitting diode is coupled to the data line to form a closed loop. The closed loop generates an induced current according to the data signal and causes the selected light emitting diode to emit light according to the induced current.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: April 20, 2021
    Assignee: Au Optronics Corporation
    Inventors: Yu-Sheng Huang, Ching-Yi Hsu, Kuan-Hsun Chen, Hong-Sian Chi
  • Publication number: 20200335030
    Abstract: A display device is provided. The display device includes a data signal transmitter and a display panel. The data signal transmitter is used to transmit data signals. A display area of the display panel is divided into sub-display areas. Each sub-display area includes light emitting diodes, a data line, column switches, and row switches. A portion of the data line is formed as a data induction coil to receive one of the data signals by wireless sensing. The display panel selects one of the light emitting diodes as a selected light emitting diode by the column switches and the row switches. The selected light emitting diode is coupled to the data line to form a closed loop. The closed loop generates an induced current according to the data signal and causes the selected light emitting diode to emit light according to the induced current.
    Type: Application
    Filed: October 20, 2019
    Publication date: October 22, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yu-Sheng Huang, Ching-Yi Hsu, Kuan-Hsun Chen, Hong-Sian Chi
  • Patent number: 10803805
    Abstract: A display panel includes a pixel structure corresponding to a display area, and a receiver antenna structure disposed on the pixel structure. The receiver antenna structure includes multiple receiver antennas providing first signals to the pixels of the pixel structure. Each receiver antenna corresponds to at least one pixel, and has an induced decibel (dB). For each receiver antenna, the induced dB is determined by multiple parameters of the receiver antenna, such as a winding number of the receiver antenna; an outer diameter of the receiver antenna; an inner diameter of the receiver antenna; a line pitch of the receiver antenna; a line width of the receiver antenna; and a line thickness of the receiver antenna. The induced dB of at least one of the receiver antennas is greater than the induced dB of other receiver antennas. The display panel may be used in a tiled micro LED display apparatus.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 13, 2020
    Assignee: A.U. VISTA, INC.
    Inventors: Wei-Min Cho, Yu-Sheng Huang, Pin-Miao Liu, Ching-Yi Hsu
  • Patent number: 10680120
    Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 9, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ching-Yi Hsu, Shih-Hao Liu, Wu-Hsi Lu, Yun-Chou Wei, Chih-Cherng Liao
  • Publication number: 20200144101
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi HSU, Pi-Kuang CHUANG, Po-Sheng HU
  • Patent number: 10636360
    Abstract: A display panel includes a pixel structure, a receiver antenna structure and a transmitter antenna structure. The pixel structure includes multiple pixels arranged in an array. The receiver antenna structure provides first signals to the pixels, and includes multiple receiver antennas. Each receiver antenna has a resonance frequency. The transmitter antenna structure transmits wireless signals to the receiver antenna structure such that the receiver antenna structure generates the first signals, and includes multiple transmitter antennas. Each transmitter antenna one-to-one corresponds to one receiver antenna and has an identical resonance frequency. The receiver and transmitter antennas are correspondingly divided into multiple receiver and transmitter antenna loop groups, and each antenna loop group includes at least 3 antennas.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 28, 2020
    Assignee: A.U. VISTA, INC.
    Inventors: Ching-Yi Hsu, Yu-Sheng Huang, Hsing-Yi Hsieh
  • Publication number: 20200082780
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung CHIN, Ching-Yi HSU, Chang-He LIU, Chih-Cherng LIAO, Jun-Wei CHEN, Leuh FANG
  • Publication number: 20200020751
    Abstract: A display panel includes a pixel structure corresponding to a display area, and a receiver antenna structure disposed on the pixel structure. The receiver antenna structure includes multiple receiver antennas providing first signals to the pixels of the pixel structure. Each receiver antenna corresponds to at least one pixel, and has an induced decibel (dB). For each receiver antenna, the induced dB is determined by multiple parameters of the receiver antenna, such as a winding number of the receiver antenna; an outer diameter of the receiver antenna; an inner diameter of the receiver antenna; a line pitch of the receiver antenna; a line width of the receiver antenna; and a line thickness of the receiver antenna. The induced dB of at least one of the receiver antennas is greater than the induced dB of other receiver antennas. The display panel may be used in a tiled micro LED display apparatus.
    Type: Application
    Filed: February 21, 2019
    Publication date: January 16, 2020
    Inventors: Wei-Min Cho, Yu-Sheng Huang, Pin-Miao Liu, Ching-Yi Hsu
  • Publication number: 20200020749
    Abstract: A display panel includes a pixel structure, a receiver antenna structure and a transmitter antenna structure. The pixel structure includes multiple pixels arranged in an array. The receiver antenna structure provides first signals to the pixels, and includes multiple receiver antennas. Each receiver antenna has a resonance frequency. The transmitter antenna structure transmits wireless signals to the receiver antenna structure such that the receiver antenna structure generates the first signals, and includes multiple transmitter antennas. Each transmitter antenna one-to-one corresponds to one receiver antenna and has an identical resonance frequency. The receiver and transmitter antennas are correspondingly divided into multiple receiver and transmitter antenna loop groups, and each antenna loop group includes at least 3 antennas.
    Type: Application
    Filed: February 18, 2019
    Publication date: January 16, 2020
    Inventors: CHING-YI HSU, Yu-Sheng Huang, Hsing-Yi Hsieh
  • Patent number: D1047917
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: October 22, 2024
    Assignee: TELEBOX INDUSTRIES CORP.
    Inventors: Fu-Wen Wu, Ching-Yi Hsu, Hung Yu Wu
  • Patent number: D1054384
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: December 17, 2024
    Assignee: TELEBOX INDUSTRIES CORP.
    Inventors: Fu-Wen Wu, Ching-Yi Hsu, Hung Yu Wu