Patents by Inventor Ching Yi Tsai

Ching Yi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12232425
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: February 18, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Publication number: 20250045941
    Abstract: A depth camera capable of measuring the oblique velocity of an object is provided, wherein a depth camera capable of measuring the lateral velocity of an object includes a depth camera body, a first configuration file, and a lateral velocity calculation system. The lateral velocity calculation system includes: first image-processing software for recording a first depth distance at which images are taken of an object and for calculating the number of pixels corresponding to a lateral movement of the object and the duration of the lateral movement; and lateral velocity calculation software for calculating the lateral velocity of the object. The depth camera capable of measuring the oblique velocity of an object allows the lateral/longitudinal/oblique velocity of an object to be measured in real time using image-related techniques.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 6, 2025
    Inventors: Wen-Hsin SUN, Jun-Yi YU, Siang-Siuan TSAI, Guan-Wei HUANG, Ching-Cherng SUN
  • Publication number: 20250035718
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen -Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20240386523
    Abstract: A computing system with graphics processor boosting is shown. The computing system has a graphics processing unit controlling a display, a code memory storing instructions, and a processor operating the graphics processing unit to control the display. The processor is configured to execute the instructions retrieved from the code memory to implement a plurality of graphics processor boosting modules for the graphics processing unit, and implement an activation controller that controls activation of the different graphics processor boosting modules through different configuration interfaces with balances between the different graphics processor boosting modules.
    Type: Application
    Filed: April 9, 2024
    Publication date: November 21, 2024
    Inventors: Po-Yu HUANG, Shih-Chin LIN, Ching-Yi TSAI, You-Ming TSAO
  • Publication number: 20240386648
    Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.
    Type: Application
    Filed: February 22, 2024
    Publication date: November 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Yu Huang, Shih-Chin Lin, Ching-Yi Tsai, You-Ming Tsao
  • Publication number: 20230390358
    Abstract: Disclosed herein is a method for alleviating depression, which includes administering to a subject in need thereof a composition containing TNFAIP3-interacting protein (TNIP) 1. The composition is administered to the CA3 region of the subject's hippocampus.
    Type: Application
    Filed: February 22, 2023
    Publication date: December 7, 2023
    Inventors: Yi-Yung Hung, Hong-Yo Kang, Ching-Yi Tsai, Ya-Ling Huang
  • Patent number: 7182901
    Abstract: An embodiment of the claimed invention includes a method of manufacturing an object. The method includes providing an object portion, providing a protrusion, forming a recess in the object portion by pressing at least a first portion of the protrusion into the object portion. In addition, a recess is formed in the object by placing material adjacent to both at least a second portion of the protrusion and at least a part of the object portion.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: February 27, 2007
    Inventors: Ming Tsai Tseng, Ching Yi Tsai
  • Publication number: 20040043536
    Abstract: A method of producing individual integrated circuit package units includes the steps of: providing a base which includes a leadframe, a plurality of package precursors, and a continuous encapsulating epoxy layer bonded integrally with the leadframe; and singulating the package precursors. The leadframe has a plurality of metallic connection bars and extension parts formed integrally with the connection bars. The package precursors are singulated by cutting the leadframe and the epoxy layer along first and second cutting streets. The cutting of the base is performed by cutting into the first and second cutting streets with a cutting tool, which can be a single-blade or dual-blade, thereby separating the connection bars from the inner leads.
    Type: Application
    Filed: August 22, 2003
    Publication date: March 4, 2004
    Applicant: Uni-Tek System, Inc.
    Inventors: Dick Hong, Dean Pan, Ching-Yi Tsai