Patents by Inventor Ching-Yih Tseng

Ching-Yih Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180183490
    Abstract: A communication receiving apparatus and a method for detecting transmit symbols are provided. In the method, received signal and channel state information corresponding to the received signal are obtained. A modified Least-Square (LS) estimation according to the received signal and the channel state information is calculated. The modified LS estimation is defined as min min w ? ? Aw ? 2 which subjects to a linearly-constrained equation CHw=x?xls, C is a constraint matrix which is a matrix multiplication of a matrix A and the channel state information matrix H, w is a variable vector, x is a vector of a transmit symbol, and xls is a LS solution according to the received signal and the channel state information. The transmit symbol is determined according to the solution of the modified LS estimation. The embodiment of the disclosure is applicable to any digitally modulated communication systems, including but not limited to Multiple Input Multiple Output (MIMO) communication systems.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventor: Ching-Yih Tseng
  • Patent number: 9942004
    Abstract: This invention discloses apparatus and methods for detecting transmit symbols from the receiving waveform samples at the receiver side for communications systems. The receiving waveform samples are corrupted by channel and noise effects and the detection is carried out with a maximum likelihood optimality criterion. This invention utilizes a successive linear constraint exchange scheme that formulates a sequence of linearly constrained minimization subproblems to allow the solutions to these subproblems, combined with certain quantization and mapping operations, to converge to the optimal maximum likelihood estimate. This invention is applicable to any digitally modulated communications systems, including but not limited to Multiple Input Multiple Output (MIMO) communications systems.
    Type: Grant
    Filed: June 11, 2016
    Date of Patent: April 10, 2018
    Inventor: Ching-Yih Tseng
  • Publication number: 20160365949
    Abstract: This invention discloses apparatus and methods for detecting transmit symbols from the receiving waveform samples at the receiver side for communications systems. The receiving waveform samples are corrupted by channel and noise effects and the detection is carried out with a maximum likelihood optimality criterion. This invention utilizes a successive linear constraint exchange scheme that formulates a sequence of linearly constrained minimization subproblems to allow the solutions to these subproblems, combined with certain quantization and mapping operations, to converge to the optimal maximum likelihood estimate. This invention is applicable to any digitally modulated communications systems, including but not limited to Multiple Input Multiple Output (MIMO) communications systems.
    Type: Application
    Filed: June 11, 2016
    Publication date: December 15, 2016
    Inventor: Ching-Yih Tseng
  • Patent number: 9385656
    Abstract: A system for reducing a mismatch between an in-phase (I) signal and a quadrature phase (Q) signal is disclosed. The system includes a phase compensation block comprising an infinite impulse response (IIR) filter configured to reduce a first portion of a mismatch between an I signal and a Q signal, wherein the first portion includes frequency selective phase mismatch. The system further includes a gain compensation block comprising a finite impulse response (FIR) filter configured to reduce a second portion of the mismatch, wherein the second portion includes frequency selective gain mismatch. The phase compensation block and the gain compensation block are calibrated at least in part based on a loopback signal, wherein the loopback signal is routed from a transmitting portion of a radio frequency (RF) circuitry back to a receiving portion of the RF circuitry.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 5, 2016
    Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Ching-Yih Tseng, Wen-Sheng Cheng
  • Publication number: 20130121388
    Abstract: A system for reducing a mismatch between an in-phase (I) signal and a quadrature phase (Q) signal is disclosed. The system includes a phase compensation block comprising an infinite impulse response (IIR) filter configured to reduce a first portion of a mismatch between an I signal and a Q signal, wherein the first portion includes frequency selective phase mismatch. The system further includes a gain compensation block comprising a finite impulse response (FIR) filter configured to reduce a second portion of the mismatch, wherein the second portion includes frequency selective gain mismatch. The phase compensation block and the gain compensation block are calibrated at least in part based on a loopback signal, wherein the loopback signal is routed from a transmitting portion of a radio frequency (RF) circuitry back to a receiving portion of the RF circuitry.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: ACROSPEED, INC.
    Inventors: Ching-Yih Tseng, Wen-Sheng Cheng
  • Patent number: 7447262
    Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 4, 2008
    Assignee: RDC Semiconductor Co., Ltd.
    Inventors: Ching-Yih Tseng, Ming-Chou Yen, Jui-Tai Ko, Kun-Ying Tsai
  • Publication number: 20080107138
    Abstract: An apparatus and method for a receiver to recognize channel numbers, skew delays, and polarities of N channels by extracting the properties of the transmitted signals are provided. Each of the N signals comprises a plurality of digital symbols with certain characteristics known to the receiver. The apparatus comprises a calculation unit, a statistic unit, and a selection unit. The calculation unit is used to compute a value for each channel according to the properties of the digital symbols captured on that particular channel within a predetermined interval. The statistic unit is used to derive a plurality of statistical values based on the values from the calculation unit. The selection unit recognizes the special property of a channel, identifies the remaining N?1 channels, compensates the skew delays, and corrects polarities.
    Type: Application
    Filed: April 24, 2007
    Publication date: May 8, 2008
    Applicant: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Ching-Yih Tseng, Yu-Chi Chen
  • Publication number: 20060256849
    Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Applicant: RDC Semiconductor Co., Ltd.
    Inventors: Ching-Yih Tseng, Ming-Chou Yen, Jui-Tai Ko, Kun-Ying Tsai