Patents by Inventor Ching-Ying Chen

Ching-Ying Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136447
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductivity type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is located under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well region.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren LAO, Hsiao-Ying YANG, Hsing-Chao LIU, Ching-Chung CHEN
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11924964
    Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
  • Publication number: 20180140072
    Abstract: A cosmetic applicator includes a tube member, a tubular seat, and a head unit. The tube member has a first end portion having a tube end surface, and a seat connector that protrudes from the tube end surface, a second end portion opposite to the first end portion, and a receiving space extending therethrough. The tubular seat is disposed on the first end portion, and has a seat end surface abutting against the tube end surface, and a seat space formed therein, extending through the tubular seat, communicating with the receiving space, and having a connecting portion rotatably engaged with the seat connector. The tubular seat is rotatable relative to the first end portion between straight and bent positions.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Inventor: Ching-Ying Chen