Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A casing includes a main body and a covering layer. The main body has a first transparent area and a second transparent area disposed as mirror images. Light passes through the first transparent area and the second transparent area. The covering layer covers the second transparent area and has a transmittance gradient. A method for manufacturing the casing and an electronic device having the casing are also disclosed.

Abstract: A method for manufacturing a photomask of cylindrical capacitor arrays surrounded by a corrugated protection trench is provided. First, a capacitor array layout is generated, next, the capacitor array patterns are copied to protection trench area with exact the same shape and pitch, finally, the protection trench is finished by filling connecting patterns between gaps of the capacitor arrays. A corrugated close loop protection trench pattern can hence be developed upon photoresist through the exposing and is developing of a photo stepper.

Abstract: A method for inspection which involves the complete and sequential removal of an aluminum containing metallization layer, and other metal and insulator layers, from the surface of a silicon substrate. The layers are removed through sequential chemical etch processes tailored specifically to the composition of the individual layers. Upon removal of all layers, the surface of the silicon substrate is etched in a buffered aqueous etchant solution. The surface of the silicon substrate may then be inspected with the aid of an optical microscope to determine level to which the aluminum containing metallization layer has spiked into the silicon substrate.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A method is disclosed for improved planarization and deposition of intermetal dielectric layers in semiconductor substrates. More specifically, the method involves the performance of specific process steps in-situ. That is, unlike in prior art, starting with cured spin-on-glass (SOG), the steps of SOG etchback and deposition of the intermetal dielectric PECVD, all take place sequentially in the same chamber and without a vacuum break. If not in the same chamber, then in the same load lock system. In this manner, it is shown that no longer does the SOG layer delaminate from the oxide layer. Furthermore, because the system is not exposed to moisture due to the absence of vacuum break, there is no adverse reaction when metal is deposited into the via holes.

Abstract: A process has been developed for removing an anti-reflective coating of titanium nitride from the surface of an aluminum layer that has been covered by a dielectric layer. Previously, this was achieved by coating said titanium nitride layer (together with the aluminum layer) with the dielectric layer and then using a single etching process to form both via holes through the dielectric and to remove the titanium nitride. When this process is used, etching proceeds reasonably quickly through the dielectric layer but becomes extremely slow once the titanium nitride is reached. In the process of the present invention, the titanium nitride layer is rapidly removed (prior to application of the dielectric layer) using a more powerful etchant. The titanium nitride/titanium layer that underlies the aluminum layer is protected during this rapid etching phase by means of a layer of a spin-on glass.

Abstract: A process has been developed in which small diameter contact holes can be filled with chemically vapor deposited tungsten, without severe attack of the contact hole liner materials. An adhesive layer of titanium, and a barrier layer of titanium nitride are used for the contact hole liner, and are deposited prior to tungsten process. A process consisting of subjecting the barrier layer of titanium nitride to a rapid thermal anneal, in an ammonia ambient, results in enhanced barrier characteristics. The robust titanium nitride layer is now able to survive the tungsten deposition process, and attack form fluorine ions, produced during the decomposition of the tungsten source, tungsten hexafluoride.

Abstract: A process has been developed that allows small diameter contact holes to be filled with chemical vapor deposited tungsten, without tungsten peeling from the sides of the contact hole. The process consists of initially depositing an adhesive layer of titanium in the contact hole, followed by a rapid thermal anneal cycle, in an ammonia ambient, for purposes of creating a thin, uniform, barrier layer of titanium nitride. The titanium nitride protects the underlying titanium adhesion layer from the by-products introduced during the tungsten deposition, specifically the evolution of fluorine ions resulting from the decomposition of tungsten hexafluoride.