Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductivity type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is located under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well region.

Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A chip bonding method for bonding a chip on a display panel is provided. The chip includes a joint face, a rear face, input bumps and output bumps. The joint face having a first symmetry axis line is opposite to the rear face. The input bumps and the output bumps are respectively located on two sides of the symmetry axis line and disposed on the joint face. The chip bonding method includes: calculating a first centroid collectively formed by contact faces of the input bumps and the output bumps, defining a straight line passing through the first centroid and parallel to the first symmetry axis line, and applying pressure on the rear face of the chip by a forcing face parallel to the joint face, wherein the forcing face has a second symmetry axis line aligned parallel to the straight line.

Abstract: A chip bonding method for bonding a chip on a display panel is provided. The chip includes a joint face, a rear face, input bumps and output bumps. The joint face having a first symmetry axis line is opposite to the rear face. The input bumps and the output bumps are respectively located on two sides of the symmetry axis line and disposed on the joint face. The chip bonding method includes: calculating a first centroid collectively formed by contact faces of the input bumps and the output bumps, defining a straight line passing through the first centroid and parallel to the first symmetry axis line, and applying pressure on the rear face of the chip by a forcing face parallel to the joint face, wherein the forcing face has a second symmetry axis line aligned parallel to the straight line.