Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures, forming a passivation layer over the top metal structures of the first interconnect structure, forming a first opening through the passivation layer, forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure, performing a circuit probe test on the probe pad, removing the probe pad, and forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to a second top metal structure of the top metal structures and a third top metal structure of the top metal structures.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Abstract: A processing unit can include a plurality of chiplets coupled in a cascade topology by a plurality of interfaces. A set of the plurality of cascade coupled chiplets can be configured to execute a plurality of layers or blocks of layers of an artificial intelligence model. The set of cascade coupled chiplets can also be configured with parameter data of corresponding ones of the plurality of layers or blocks of layers of the artificial intelligence model.

Abstract: A portable article includes a portable item having a primary function and adapted for being conveniently carried by a user, and an alert timer, which is built-in with the portable item, including a time setter setting a time interval at a starting time, a time processor counting the time interval starting from the starting time, and a signal generator automatically and timely generating an alert signal in a punctual time manner when said time processor is finished counting the time interval in responsive to the starting time.

Abstract: A timepiece includes a time provider providing a current time and an alert timer. The alert timer includes a time setter setting a time interval at the current time as a starting time, a time processor counting the time interval starting from the starting time, and a signal generator automatically and timely generating an alert signal in a punctual time manner when said time processor is finished counting the time interval in responsive to the starting time.

Abstract: An image compression/decompression method is provided for compressing/decompressing image data. First, each pixel of the raw image data is received. Then, each pixel of the raw image data is compared with a default transparent code to recognize whether the pixel in the raw image data is a transparent code pixel. Finally, a single transparent code pixel or one transparent code pixel of a sequence of transparent code pixels is stored, and a total length information of the single transparent code pixel or the sequence of the transparent code pixels is acquired.