Patents by Inventor Ching-Yu Lai

Ching-Yu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134279
    Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Patent number: 11955336
    Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing Hong Huang, Wei-Han Lai, Ching-Yu Chang
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240096623
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.
    Type: Application
    Filed: March 17, 2023
    Publication date: March 21, 2024
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11914301
    Abstract: A photoresist includes a polymer and a photoactive compound. The photoactive compound contains a sensitizer component. The photoactive compound contains an acid generator or a base molecular. The acid generator or the base molecular bonds the sensitizer component. The photoactive compound is within a polymer backbone. The sensitizer component is configured to absorb an EUV light to produce electrons.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hsin Hsieh, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 8245195
    Abstract: A method for debugging a computer program is provided. The method pushes a plurality of registers into a stack, and calculates a jump-from address and a jump-to address for each jump according to values of the registers. The jump-from address and the jump-to address are then stored into a storage system. The method may monitor the execution of the computer program in system management mode (SMM).
    Type: Grant
    Filed: December 7, 2008
    Date of Patent: August 14, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ching-Yu Lai
  • Publication number: 20090172642
    Abstract: A method for debugging a computer program is provided. The method pushes a plurality of registers into a stack, and calculates a jump-from address and a jump-to address for each jump according to values of the registers. The jump-from address and the jump-to address are then stored into a storage system. The method may monitor the execution of the computer program in system management mode (SMM).
    Type: Application
    Filed: December 7, 2008
    Publication date: July 2, 2009
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHING-YU LAI