Patents by Inventor Ching Yuan

Ching Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11993066
    Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
  • Patent number: 11984465
    Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Yen-Ting Chiang, Chun-Yuan Chen, Shen-Hui Hong
  • Patent number: 11984261
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20240153987
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20240143050
    Abstract: A portable electronic device includes a housing, a heat-dissipation component, a bracket, a door structure, a driving mechanism, and a driven linkage. The housing includes a heat-dissipation opening disposed in the housing. The bracket is disposed in the housing and surrounds the heat-dissipation component. The door structure is configured to move between a closed position covering the heat-dissipation opening and an open position exposing the heat-dissipation opening. The driving mechanism is coupled between the bracket and the door structure to drive the door structure to rotate and move. The driven linkage is coupled between the bracket and the door structure. When the door structure is driven to rotate and move, the door structure drives the driven linkage to rotate and move, so that the driven linkage and the driving mechanism jointly drive the door structure to move between the closed position and the open position.
    Type: Application
    Filed: June 13, 2023
    Publication date: May 2, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Cheng-Han Chung, Hung-Yueh Chen, Ching-Yuan Yang
  • Patent number: 11967591
    Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
  • Publication number: 20240122528
    Abstract: A system for monitoring sepsis in a healthcare facility. The system calculates sepsis scores for a patient using physiological parameter data captured by one or more sensors. The system generates a sepsis score trend based on the sepsis scores, and generates a predicted sepsis trend based on the sepsis scores and a treatment administered to the patient. The system displays the predicted sepsis trend over the sepsis score trend. The system can further display a summary including a sepsis status and a treatment status for a plurality of patients in the healthcare facility.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chiew Yuan Chung, Christopher L. Long, Craig M. Meyerson, Rebecca Quilty-Koval, Eugene G. Urrutia, Swathi Utukuri, Ching Yue Yeung
  • Publication number: 20240128381
    Abstract: A power diode device includes a substrate. The substrate includes a core layer of a first conductive type, a first diffusion layer of the first conductive type, a second diffusion layer of a second conductive type, and a heavily doped region of the second conductive type. The core layer is located between the first diffusion layer and the second diffusion layer. A thickness of the core layer is greater than that of the second diffusion layer. The heavily doped region is located in the second diffusion layer and extends toward the core layer to form a PN junction between the heavily doped region and the core layer. A method for manufacturing the power diode device is also provided.
    Type: Application
    Filed: June 2, 2023
    Publication date: April 18, 2024
    Inventors: Ching Chiu TSENG, Tzu Yuan LO, Chao Yi CHANG
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11948949
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
  • Publication number: 20240100743
    Abstract: A separation apparatus suitable for separating plastic and silicone in a composite material includes a storage tank configured to store a hydrocarbon solvent, and a reaction tank fluidly connected to the storage tank and having a reaction space for placement of the composite material therein and for receiving the hydrocarbon solvent from the storage tank such that the composite material is immersed in the hydrocarbon solvent for separating the plastic and the silicone in the composite material. The plastic and the silicone in the composite material are insoluble in the hydrocarbon solvent.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Applicants: Taiwan Green Point Enterprises Co., Ltd., Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Bing-Yuan Lin, Ying-Yin Chen, Yung-Chih Chen, Ching-Hsin Chen
  • Publication number: 20240105744
    Abstract: An image sensor includes a photoelectric conversion layer, a plurality of deep trench isolations, a first color filter, a first deflector, and a covering layer. The photoelectric conversion layer includes a first photodiode and a second photodiode. The deep trench isolations separate the first photodiode and the second photodiode, in which a pixel dimension is determined by a distance between two adjacent deep trench isolations. The first color filter is disposed on the first photodiode and the second photodiode. The first deflector is disposed on the first color filter. The covering layer covers and surrounds the first deflector. A refractive index of the covering layer is greater than a refractive index of the first deflector, and a difference value between the refractive index of the covering layer and the refractive index of the first deflector is in a range from 0.15 to 0.6.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Ching-Hua LI, Chun-Yuan WANG, Zong-Ru TU, Po-Hsiang WANG
  • Publication number: 20240107780
    Abstract: A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 28, 2024
    Inventors: Chih-Wei WU, Ying-Ching SHIH, Wen-Chih CHIOU, An-Jhih SU, Chia-Nan YUAN
  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240096546
    Abstract: A magnetic member includes a bobbin, a coil and a magnetic core. The bobbin includes a first portion and a second portion. The second portion is connected to the first portion and includes a thermoplastic material. The first portion includes an insulating material that is different from the thermoplastic material. The coil is wound on the first portion of the bobbin and includes a terminal end fixed at the second portion of the bobbin. The magnetic core is disposed on the bobbin and extends through the bobbin.
    Type: Application
    Filed: March 9, 2023
    Publication date: March 21, 2024
    Inventors: Cai-Li GU, Chun-Ching YEN, Xiao-Xia YUAN, Chih-Ho LAI, Shao-Dong ZHANG
  • Publication number: 20240088030
    Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Liang CHEN, Chi-Yu LU, Ching-Wei TSAI, Chun-Yuan CHEN, Li-Chun TIEN
  • Patent number: 11916100
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20240064938
    Abstract: A handheld electronic device is provided. The handheld electronic device includes a screen, a back cover, a frame, a main board, and a heat conduction structure. The frame is arranged between the screen and the back cover. The frame and the back cover define a space. The main board is arranged in the space, and includes a front surface and a back surface. The front surface faces the screen and includes a heat source. The heat conduction structure extends from the front surface to the back surface, and includes a first end and a second end opposite to each other. The first end is arranged at the heat source, and the second end extends to the back cover.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 22, 2024
    Inventors: Chien-Feng CHUNG, Ching-Yuan YANG, Chih-Yao KUO, Cheng-Han CHUNG
  • Patent number: 11903169
    Abstract: The disclosure provides a portable electronic device, including: a housing, a heat dissipation component, a bracket, a cover structure, and a plurality of pivotal linkage rods. The housing includes a heat dissipation opening. The heat dissipation component is disposed in the housing and corresponds to the heat dissipation opening. The bracket is disposed in the housing and encloses the heat dissipation component. The cover structure is configured to move between a close position covering the heat dissipation opening and an open position exposing the heat dissipation opening. Each of the plurality of pivotal linkage rods is pivotally connected between the bracket and the cover structure, and is configured to be driven to rotate, to drive the cover structure to move between the close position and the open position.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: February 13, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Cheng-Han Chung, Ching-Yuan Yang, Chui-Hung Chen
  • Patent number: 11901791
    Abstract: A functional module is provided. The functional module is applied to an electronic device, and includes a housing, a functional member, and a motor assembly. Both the functional member and the motor assembly are disposed in the housing. The motor assembly includes a motor and an output shaft. The motor is configured to drive the output shaft to rotate. The output shaft protrudes from one side of the housing.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 13, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chia-Min Cheng, Chui-Hung Chen, Ching-Yuan Yang, Cheng-Han Chung