Abstract: A device for hydrogen production with waste aluminum includes a treatment apparatus for waste aluminum and a reaction tank. The apparatus includes a first crusher, a pickling tank, and a second crusher. The first crusher is for preliminarily crushing waste aluminum to obtain first aluminum chips. The pickling tank is for receiving and pickling the first aluminum chips crushed by the first crusher. The second crusher is for receiving and fine crushing the first aluminum chips to obtain second aluminum chips. The second aluminum chips are received by the reaction tank and then hydrolyzed with an alkaline solution in the reaction tank to produce hydrogen. Since waste aluminum is used as the raw material of hydrogen production, and a specific device is used for waste aluminum treatment, so the effects of recovering waste metal, reducing environmental damage, and saving costs can be achieved at the same time.

Abstract: A method for forming a metal bump is provided. Firstly, a photo-resist layer is formed on an IC chip by using a lithographic process. The photo-resist layer comprises a metal bump reserved groove and a metal bump slit reserved portion with the extent covering a metal pad. The metal bump slit reserved portion is formed on the metal pad and within the metal bump reserved groove. Then, a deposition process is applied to form the metal bump in the metal bump reserved groove and have the metal bump slit reserved portion penetrating the metal bump. Afterward, the photo-resist layer is removed to leave the metal bump with a metal bump slit therein.

Abstract: A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.

Abstract: A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric layer corresponding to the first metal conductive line. Then, a metal plug is formed in the contact window. The metal plug is used as a mask for etching the semiconductor device, such that the etched semiconductor device takes the form of a shape corresponding to the metal plug. Through the manufacturing method, the semiconductor device is formed according to the shape of the metal plug and is completely aligned with the metal plug.

Abstract: A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

Abstract: A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric layer corresponding to the first metal conductive line. Then, a metal plug is formed in the contact window. The metal plug is used as a mask for etching the semiconductor device, such that the etched semiconductor device takes the form of a shape corresponding to the metal plug. Through the manufacturing method, the semiconductor device is formed according to the shape of the metal plug and is completely aligned with the metal plug.

Abstract: A magnetic random access memory with reduced currents in a bit line and a manufacturing method thereof. In one embodiment, the memory includes a bottom electrode, a first dielectric layer on the bottom electrode, a via in the first dielectric layer, a magnetic tunnel junction (MTJ) element that is aligned with and formed on a via, and a metal layer that is formed on and in contact with an MTJ element. In another embodiment, a second dielectric layer is formed on the first dielectric layer, and a metal layer is formed on and in contact with an MTJ element and the second dielectric layer. These designs can protect the MTJ element from damage during the etching process. Hence it increases the stability and the yield rate during the manufacturing process. Furthermore, the designs can reduce the current requirements of running magnetic cells, thereby reducing power consumption.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate having a dielectric layer formed thereon, wherein an opening exposing a pad area for connection with other structures is also formed in the dielectric layer. Next, a glue layer is formed over the pad area and the dielectric sidewalls of the opening. Subsequently, plug material is deposited into the opening forming a plug layer. This is followed by etching back the plug layer to return the plug material inside the opening to a level below the height of the dielectric layer. Then, a selective etching method having a high selectivity ratio between the dielectric layer and the plug layer is used to etch the dielectric layer. Finally, the dielectric layer and the plug layer are etched to almost the same level of height.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate, then forming a dielectric layer having an opening that exposes a pad area for connection with other structures. Next, a glue layer is formed lining the opening and the dielectric layer. Subsequently, plug material is deposited into the opening to form a plug layer. This is followed by etching back the plug layer to a level higher than the glue layer that formed on the top of the dielectric layer. Thereafter, a metallic layer is formed over the plug layer, and a photoresist layer is then coated over the metallic layer. The metallic layer and the plug layer are then patterned by etching such that the plug layer is turned a plug. The characteristic of this invention lies in retaining a portion of the plug layer after the first etching such that the etched plug layer is at a level higher than the glue layer.