Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: In a method of manufacturing a semiconductor device, in an EUV scanner, an EUV lithography operation using an EUV mask is performed on a photo resist layer formed over a semiconductor substrate. After the EUV lithography operation, the EUV mask is unloaded from a mask stage of the EUV scanner. The EUV mask is placed under a reduced pressure below an atmospheric pressure. The EUV mask is heated under the reduced pressure at a first temperature in a range from 100° C. to 350 C°. After the heating, the EUV mask is stored in a mask stocker.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: The present disclosure provides a mask for photolithography patterning. The mask includes a substrate, a pattern layer on a surface of the substrate. The mask also includes a pellicle attached to the substrate and configured to isolate the pattern layer from ambient. The pellicle includes a membrane between the pattern layer and ambient, a frame for securing the membrane on the substrate, and an optical member disposed in the membrane. A method for manufacturing the mask is also provided.

Abstract: An apparatus includes a developing tank, and the developing tank has a sidewall and a bottom. A fluid manifold is adjacent the bottom of the developing tank. The fluid manifold includes a plurality of holes and a plurality of valves. Developer and rinsing fluid flow through the plurality of holes. Each of the plurality of the valves corresponds to a different hole of the plurality of holes, and the plurality of valves allow the developer and the rinsing fluid to flow through the holes when open and prevent the developer and the flowing liquid from flowing through the holes when closed. The developer flows through a developer inlet to the fluid manifold. The rinsing fluid flows through a rinsing fluid inlet to the fluid manifold. A controller is configured to individually control opening and closing of each of the plurality of valves.

Abstract: The present disclosure provides a mask for photolithography patterning. The mask includes a substrate, a pattern layer on a surface of the substrate. The mask also includes a pellicle attached to the substrate and configured to isolate the pattern layer from ambient. The pellicle includes a membrane between the pattern layer and ambient, a frame for securing the membrane on the substrate, and an optical member disposed in the membrane. A method for manufacturing the mask is also provided.

Abstract: An apparatus includes a developing tank, and the developing tank has a sidewall and a bottom. A fluid manifold is adjacent the bottom of the developing tank. The fluid manifold includes a plurality of holes and a plurality of valves. Developer and rinsing fluid flow through the plurality of holes. Each of the plurality of the valves corresponds to a different hole of the plurality of holes, and the plurality of valves allow the developer and the rinsing fluid to flow through the holes when open and prevent the developer and the flowing liquid from flowing through the holes when closed. The developer flows through a developer inlet to the fluid manifold. The rinsing fluid flows through a rinsing fluid inlet to the fluid manifold. A controller is configured to individually control opening and closing of each of the plurality of valves.

Abstract: The present disclosure provides a mask for photolithography patterning. The mask includes a substrate, a pattern layer on a surface of the substrate. The mask also includes a pellicle attached to the substrate and configured to isolate the pattern layer from ambient. The pellicle includes a membrane between the pattern layer and ambient, and an optical member disposed in the membrane. A method for manufacturing the mask is also provided.

Abstract: An apparatus for generating a laminar flow includes an injection nozzle and a suction nozzle. The injection nozzle and the suction nozzle are operable to form the laminar flow for blocking particles from contacting a proximate surface of an object. The injection nozzle includes a main outlet to blow out the laminar flow. The injection nozzle is configured to generate a Coanda flow along an external surface of the injection nozzle. The suction nozzle is configured to provide a gas pressure gradient for the laminar flow.

Abstract: To facilitate LWA PDCP setting/scheduling, a method of providing dynamic PDCP status report polling is proposed. To enhance scheduling efficiency, the transmitter (can be eNB from DL or UE for UL) can dynamically poll PDCP status report for LWA behavior. The polling can be done by a standalone PDCP control PDU or use reserved bit in PDCP data PDU. The triggering condition for PDCP status polling includes: PDCP without poll time exceeds a first threshold, PDCP without poll bytes exceeds a second threshold, PDCP without poll PDU numbers exceeds a third threshold, a data buffer is empty, and when LWA is deactivated.

Abstract: An apparatus includes a developing tank and a fluid manifold in the bottom of the developing tank. The fluid manifold includes a plurality of holes through which developer flows and a plurality of valves corresponding to the plurality of holes. The valves allow developer to flow through the holes when open and prevent developer from flowing through the holes when closed. A trench surrounds the fluid manifold through which developer is drained from the developing tank. A controller is configured to control opening and closing of the valves. In an embodiment, the apparatus includes a clamping mechanism configured to insert the substrate into and remove the substrate from the developing tank.

Abstract: The present disclosure provides a mask for photolithography patterning. The mask includes a substrate, a pattern layer on a surface of the substrate. The mask also includes a pellicle attached to the substrate and configured to isolate the pattern layer from ambient. The pellicle includes a membrane between the pattern layer and ambient, and an optical member disposed in the membrane. A method for manufacturing the mask is also provided.