Abstract: A power-up detection circuit to produce a power-up detection signal detects a reference voltage of a device. After a power-up detection has been produced, a DC current path to ground is established to conduct DC current to reset the power-up detection circuit to produce a subsequent power-up detection signal.

Abstract: A mixed-signal processor (MSP) chip with a flexible serial interface which simultaneously accommodates two serial ports on a reduced number of pins. The pin definitions of these serial ports are configured to function well with several different external chips. Any two of these chips, or two of any one of these chips, may be used concurrently by the present MSP. When used with chips that require it, the present MSP chip provides a clock signal to each of these. When used with other chips, the MSP will can receive a clock signal from an external chip, and will then pass this signal through to any chip on the other of the two serial ports.

Abstract: A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Abstract: A circuit arrangement includes a charge pumping circuit (25) and a signal-transition-detection circuit (27). The charge pumping circuit is responsive to high and low level logic signals, for alternately storing charge in a pumping capacitor (34) and transferring the stored charge from the pumping capacitor to a load (22). The signal-transition-detection circuit is responsive to both negative-going and positive-going input signal transitions (RL1) for producing and applying to the charge pumping circuit full-cycle logic signals (VPPTD). Plural signal-transition-detection circuits (27 and 57) can be used in tandem to increase benefits to the circuit arrangement.

Abstract: A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

Abstract: An integrated circuit substrate bias pumping arrangement includes a charge pump circuit arranged as a circuit path from an oscillator input to a substrate. The charge pump circuit operates to supply charge to the substrate in response to a level of the oscillator signal. In the charge pump circuit, a pumping transistor transfers stored charge from a pumping capacitor to the substrate without imparting all of a threshold voltage of the pumping transistor as a voltage loss. The pumping transistor has its conduction path connected in a series circuit between the pumping capacitor and the substrate. A control gate electrode of the pumping transistor is bootstrapped to turn on the pumping transistor by a delayed version of the input signal used for pumping stored charge from the pumping capacitor to the substrate. Two of the charge pump circuits can be operated in a push-pull configuration, substrate bias pump.

Abstract: A multiplier circuit multiplies a reference voltage to increase the level of the reference voltage. A feedback circuit of the multiplier circuit stabilize the multiplier circuit such that a feedback voltage of said feedback circuit tends to equalize the reference voltage. The feedback circuit is free from capacitance which would unstabilize the feedback circuit. A voltage divider outside of the feedback circuit reduces the multiplied voltage of the multiplier circuit.

Abstract: A circuit to provide a burn-in reference voltage that is stable with respect to temperature and manufacture. The burn-in reference voltage circuit produces a burn-in reference voltage related to an external reference voltage. The circuit includes a feedback circuit to produce a feedback voltage that tends to the internal reference voltage in response to a deviation of the feedback voltage, from the internal voltage. The feedback voltage is mirrored to produce a mirrored voltage having the same magnitude as the feedback voltage but measured with respect to the external reference voltage.

Abstract: A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.

Abstract: A crystal-stabilized integrated-circuit oscillator which uses a filtered analog coupling to automatically disable the bias current to an auxiliary gain after startup. Positive feedback is used to ensure that the switchover is completed once it starts. Thus the device sizes and biases of the primary gain stage can be selected for very low-power operation, while assuring that the oscillator will always start-up whenever poser is valid.

Abstract: A burn-in detection circuit include a first divider circuit to divide a first reference to form a divider voltage. A comparator compares the divider voltage with a second reference voltage to reduce the divider voltage based on the comparator. The comparator include a second divider circuit to be switched in parallel with a portion of said first divider circuit.

Abstract: A circuit is designed for regulating a power supply voltage. A regulator circuit (26) compares a power supply sample voltage VAR.sub.1 (34) and a reference voltage VREF (20) and corrects the power supply voltage VAR.sub.0 (30). The regulator circuit rate for correcting the power supply voltage varies with the regulator circuit power consumption. A circuit (160), responsive to a control signal (164), changes the regulator circuit power consumption.

Abstract: In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type diffusion lying between the oxide isolators in the P type region. When the N type regions are phosphorus doped deep N- regions biased at different potentials and the P type region is a boron doped P- region, a shallow P+ boron region within the P- region acts as a blocking mechanism to prevent phosphorus from piling up at the semiconductor surface and shorting the two N- regions. The channel stop may be manufactured without adding additional steps to a CMOS process flow. The oxide isolators may be formed when the oxide isolator over the inverse moat separating the P tank and the N tank is created. The P+ region within the channel maybe formed when the sources and drains for transistors within the N tank are formed.

Abstract: A RAS input disable circuit receives a power up detection signal and an internal reference signal to produce a RAS input disable signal to indicate memory access. The RAS input disable circuit eliminates a DC current path, established before the RAS input disable signal is produced.

Abstract: In a semiconductor device, an on chip coaxial cable reduces noise from adversely affecting a signal transmitted by a signal conductor. The signal conductor lies within and is isolated from a second conductor. A dielectric, such as oxide, may provide isolation. In multi level metal devices, such as double level metal devices, the signal conductor can be formed of a first level of metal and a portion of the second conductor can be formed of the first level of metal also. After forming a first level of metal, it is patterned to separate the first signal conductor from a first conductive noise shield and a second conductive noise shield. A second level of metal and a conductive level of material such as polysilicon can complete formation of the second conductor. Oxide insulators can provide isolation between the signal conductor and the second conductor by lying between the top conductive noise shield and the signal conductor and by lying between the bottom conductive noise shield and the signal conductor.

Abstract: A circuit to generate a power up reset pulse for a semiconductor device, such as a dynamic random access memory (DRAM) that may utilize an on chip voltage generator is disclosed. The circuit generates a positive going pulse when the external power supply ramps up. The pulse disappears when the voltage level within the device reaches a predetermined value of the external supply voltage. The circuit includes a CMOS inverter that is biased between the external voltage and ground and has its input coupled to the internally regulated voltage. The gate of a pull down transistor may couple the input of the CMOS inverter to the internally regulated voltage. A pull up transistor that is biased by the external voltage and whose gate is connected to the output of the CMOS inverter, is connected to the input of the CMOS inverter. Other elements may be added to enhance the circuits performance.

Abstract: A substrate bias detection circuit is disclosed. The circuit includes first and second transistors, where the first transistor has its source coupled to the substrate and where the second transistor has its source coupled to a common potential (i.e., ground). The gate and drain of the first transistor are connected together, and to the gate of the second transistor. Load devices are connected between the drains of the first and second transistors and a bias potential from a power supply node. The threshold voltages of the first and second transistors may be different, with the difference determining the voltage that the substrate must reach, relative to the common potential, to cause the circuit to respond. Upon the substrate reaching a voltage sufficient to turn the second transistor on, the drain of the second transistor will be pulled toward the common potential, indicating loss of substrate bias.

Abstract: An integrated circuit that is useful as a buffer is disclosed. The integrated circuit has an input voltage shifter circuit for shifting an input voltage and an output voltage shifter circuit for shifting an output voltage. It has a first comparator circuit for comparing the input voltage to the output voltage and a second comparator circuit for comparing the shifted input voltage to the shifted output voltage. The first comparator circuit produces a first control signal and the second comparator circuit produces a second control signal. A voltage driver circuit receives the control signals and produces the output voltage. A capacitor to compensate the output voltage can be connected to the output voltage before it is applied to the first comparator circuit and to the output voltage shifter circuit.