Abstract: A lower substrate for a liquid crystal display device and the method of making the same are disclosed. The method includes steps of: (a) providing a substrate; (b) forming a patterned transparent layer having plural recess on the substrate; (c) forming a first barrier layer on the surface of the recess; (d) coating a first metal layer on the first barrier layer and making the surfaces of the first metal layer and the transparent layer in substantially the same plane; and (e) forming a first insulated layer and a semi-conductive layer in sequence. The method further can optionally comprise the steps of: (f) forming a patterned second metal layer, wherein part of the semi-conductive layer is exposed, thus forming the source electrode and the drain electrode; and (g) forming a transparent electrode layer on part of the transparent layer and part of the second metal layer.

Abstract: A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase the transmission rate of the driving signal. Hence, the increasing yield of products can reduce the cost of manufacturing, and can meet the requirement of the large-size and high-definition thin film transistor liquid crystal display device.

Abstract: A manufacturing method for a pixel structure is provided. The method includes the following steps. A first photomask is used to form a source/drain on a substrate. A second photomask is used twice to form a transparent conductive layer and a channel layer on the substrate respectively. The transparent conductive layer covers a portion of the source/drain and is electrically connected with the same, and the pattern of the transparent conductive layer and the pattern of the channel layer are complementary patterns. Then, a dielectric layer is formed over the substrate to cover the transparent conductive layer and the channel layer. A third photomask is used to form a gate on the dielectric layer.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards, the second metal layer is manufactured to have two different thicknesses by using a photolithographic process. After that, a planar layer is formed on the second metal layer and then the planar layer is etched until part of the second metal layer is exposed. Finally, a patterned transparent electrode layer is formed on the second metal layer.

Abstract: A method for manufacturing a pixel structure is provided. A first conductive layer is formed on a substrate and patterned using a first mask to form a gate. A dielectric layer is formed over the substrate to cover the gate. A semiconductor material layer and a second conductive layer are sequentially formed over the dielectric layer. The second conductive layer is patterned using a second mask to form a pixel electrode. A patterned photo-resist layer is formed by using the first mask again such that the semiconductor material layer above the gate is protected. The semiconductor material layer is patterned to form a semiconductor layer using the pixel electrode and the patterned photo-resist layer as an etching mask. The patterned photo-resist layer is removed. A third conductive layer is formed and patterned to form a source/drain by using a third mask. The drain is electrically connected to the pixel electrode.

Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Abstract: Voltage dividing resistors (R1a, R1b, R2a, R2b) are connected in parallel with diode connected bipolar transistors (Q1, Q2) for splitting the voltage to the inputs of an operational amplifier (62, 82). Current is provided to this arrangement by current sources (I1, I2). When the supply voltage is about 0.85 volts, a temperature insensitive reference voltage of about 200 millivolts is available at the drain of a second transistor (M2, M2).

Abstract: An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole. Then, a bottom antireflective coating (BARC) layer is formed to fill the sunken portion and cover the entire surface of the polysilicon layer. Next, in a first etching step, the BARC layer outside the sunken portion of the polysilicon layer is removed and the BARC layer in the sunken portion of the polysilicon layer is retained to flatten the bottom of the sunken portion.