Abstract: A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

Abstract: A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

Abstract: A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.

Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

Abstract: An application specific integrated circuit (ASIC) including a phase-locked loop (PLL) circuit operably coupled to an internal clock and an external clock. The present PLL circuit includes an internal phase detector circuit, an internal charge pump operably coupled to the phase detector circuit, a loop filter operably coupled to the charge pump, and an internal programmable voltage-controlled oscillator 200, 300. The internal programmable voltage controlled oscillator includes a plurality of delay elements, which have a respective switch to turn-on the delay elements. A storage device having a plurality of outputs providing selected switch signals to the voltage oscillator program one of a plurality of center frequencies. Each of the outputs is operably coupled respectively to the delay elements through the respective switch. The switch isolates a first group of delay elements from a second group of delay elements.

Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

Abstract: A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

Abstract: A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.